Separate topic: Is there a standard way for specifying pins for parsing and code generation? In particular for hw/sw co-design.
There's pcf (physical constraints file) for FPGAs (e.g. https://github.com/cliffordwolf/picorv32/blob/master/picosoc...).
There's CMSIS-SVD to describe register maps for peripherals, which is useful, but not exactly what you're describing.