1. It uses two clocks, both derived from the PLL from an onboard 16Mhz MEMs oscillator: 48Mhz for usb (the usb<->serial bridge is implemented in the fpga fabric) and 24Mhz for the vga pixel clock (25.175 would be the 640x400@70Hz standard, but I compromised by dividing the usb clock by two). Using a usb<->3.3v serial cable or an fpga board w/external usb<->serial bridge you could run everything @25.175Mhz (and save half the logic in the FPGA and a kB or embedded RAM).

2. I will have to measure this and get back to you, but can't be too much, and negligible compared to the monitor in any case.

I can tell you that it's powered by a USB port and has onboard 3.3V & 1.2V regulators (300 mA & 150 mA max respectively). It doesn't currently implement a standby mode, but for reference the FPGA supports a standby mode which comsumes about 21uA according to the datasheet.

On #1, the files note a 16MHz clock, plus separate clocks for usb and vga.