It's really impressive to me how big of an improvement AMD has made under the exact same constraints as last generation. Same process (even down to the same PDK) though generally higher yields probably let them choose higher bins. Same exact chiplet size to mount to the same substrate. Same power availability. Same IO die with same interfaces and memory controller. Yet they achieve +19% IPC and higher frequency with just design changes. I wish there were more detailed information available about what day-to-day engineering work goes into these design changes. Speculating:
- Designing better workload and electrical simulations to make better decisions when evaluating changes. - Running lots of simulations to determine the optimal size and arrangement of each cache. - Improving CPU binning processes and data, improving on-die sensors, and improving boost algorithms to reliably run closer to the edge. - Tweaking parameters of automated layout algorithms to reduce area of specific functional units. - Improving the algorithms implemented in logic for various processes.