What little we've seen of x86 micro ops (the great work reverse engineering the k10 microcode), shows that the micro ops look very much like x86 instructions. Still predominantly two address, RMW instructions for instance. Very similar to the original 8086's microcode structure rather than some reaction to the RISC movement, despite the common trope to state the contrary.

Can't wait to see more information about the goldmont microcode work to see if that holds for intel as well as it does for AMD.