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Comment by Tuna-Fish | Hacker News Reader

Note that the 6900xt benchmark was running in "rage mode", and therefore was not inside 300W. Then again, the card they are comparing to is ~380W, so there is some room to play with while still being more power-efficient than the competition.

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"Rage" mode, what a nice name choice coming from ex-ATi :)

Also important to note that it had Smart Memory Access on, which requires a Ryzen CPU (and furthermore, did they say specifically a Ryzen 5xxx CPU?)

They said Ryzen 5xxx and x570 chipset.

500 series, that would cover B550.

Which is Intel level of dubious fake market segmentation considering those are no longer Chipsets, but rather southbridges sitting away from main PCIE lanes and memory buses.

A possible plausible explanation is that AMD's SAM is "just" that they fixed the BAR size limits so the entire vram can be mapped at once, instead of the still weirdly common & low 256MB limit. If so, that would actually involve the chipset (even if it's just the supporting BIOS & microcode) and not just the CPU.

But there is no chipset. PCIE controller is on CPU die.

The software that runs the PCIE controller isn't on the CPU, though. And at least at launch only the 500 series chipsets support the Ryzen 5000 CPUs. Maybe this will come to the 400 series chipsets later that get Ryzen 5000 support, or maybe this is something that was cut to squeeze in Ryzen 5000 support for the 400 series chipsets.

Where do you suppose its running then? Its pure market segmentation with AMD dictating what runs where

totally incompatible: https://www.itworldcanada.com/article/amd-zen-3-processors-w...

erm, we means totally compatible!!1: https://www.tomshardware.com/news/amd-reverses-course-will-e...

"chipset" nowadays is just a pcie device providing legacy ports (USB 2.0, additional USB 3, SATA, HDA audio controller, PCIe bridge, I2C, SPI, LPC, bunch of GPIOs).

I wonder if Smart Memory is even using PCIe 4? Remember AMD uses the PCIe lanes for interconnect between two EPYC CPUs. It's supposedly very similar to PCIe but a bit higher speed.

Smart Memory could then be as efficient as cross-CPU EPYC memory access. Which is pretty good.

Smart Memory Access is just marketing speak for resizable BARs (https://docs.microsoft.com/en-us/windows-hardware/drivers/di...)

At this point SAM seems to be Ryzen 5xxx "exclusive".

Makes me wonder if that's related to the improved L3 cache access of Zen 3?

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