From what little I’ve seen in this space, FPGAs have not made large inroads in the ML space or datacenters in general. This seems partly due to their inefficient nature compared to ASICS and moreover their software.
Unless AMD is planning something really ambitious (e.g., true software-based hardware reconfiguration that doesn’t require HDL knowledge) and are confident they’ve figured it out, I’m not sure what they hope to achieve here.
I don't know that they have actually made large inroads into those spaces, but Xilinx is indeed pushing hard for that. For years now.
This has been a holy grail for at least two decades. Its very much like asking for a programming language that can be used by non-programmers.
What in the world FPGAs have to do in a datacentre?
Think ML, networking and other such uses...
In our future datacentre we want to say how many cores, connected to how much ram, how much GPU resource, some NVME etc. etc. and there's going to be a whole lot of very specialised switching and tunnelling going on. This needs to be as close to the cores/cache as possible, a good order of magnitude faster than we run our present networking stuff, and probably an area where there will be a significant pace of development ie a software defined solution would be nice.
So, a software defined north bridge, in essence. And an FPGA is pretty much the only thing we have right now that could do the job.