How the bootstrap load made the historic Intel 8008 processor possible | Hacker News Reader

How the bootstrap load made the historic Intel 8008 processor possible

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Another fantastic post! Just one minor point for anyone just browsing the title - bootstrap loads were of course also used in 4004 which preceded the 8008.

Bootstrap loads get a mention in Federico Faggin's presentation on the 4004 at the 35th anniversary CHM presentation - it's a really interesting and engaging talk.

https://www.youtube.com/watch?v=j00AULJLCNo&t=26m0s

I think it's reasonably clear without bootstrap loads and the other innovations that Dr Faggin pioneered then Intel wouldn't have had the early lead in the microprocessor market which they were able ultimately to convert in a dominant position with x86.

I found one surprise after another in

https://ethw.org/Oral-History:Federico_Faggin

That Intel had to be physically dragged into microprocessors was a revelation. If they had not had this side-project 8080 that they considered absolutely uninteresting, when the memory business collapsed, there would be no Intel, and Andy Grove would not have become a big cheese.

Also, that self-aligned gates, depletion loads, the 8008 and 8080 were all Faggin's projects.

It is an enduring mystery why the 8080 was designed into so many systems. It was such a bad component: it couldn't do anything without a bunch of other support chips from Intel. And the ISA was so bad: half the instructions in a program were just to correct for the other instructions that didn't do the right thing.

People insisted it was great that it had these support chips, that you didn't even need for other CPUs. I thought it was because Intel had sharper sales people, but apparently not. So it remains a mystery.

Grove's infamous 'sign-in' sheet was one of the reasons that Faggin left Intel (after which they wrote him out of the story in official publications - Ted Hoff became the sole 'inventor' of the microprocessor) and of course the Z80 became much much more successful than the 8080 or 8085. Intel got very lucky with the 8088 and the IBM PC especially given the disaster that was the iAPX432.

In case you haven't seen it this looks like a very interesting interview with FF from 1995 - not watched it all yet but some interesting comments on the 8080.

https://exhibits.stanford.edu/silicongenesis/catalog/gr768wf...

I had no idea he was behind Synaptics, or that Synaptics was using Mead's analog computation architecture in 1995.

Author here for all your 8008 questions :-)

I love these posts and I could probably ask a thousand questions. I'll constrain myself to just... a couple. :)

Does the 8008 get ground internally or does the IO just drive Vdd (-9V) as the low level? The data sheet you linked to has no min for Vol so I am guessing that it does but it seems like that would make interfacing to peripheral ICs kind of annoying (assuming TTL levels). All the pinouts I found online [1] have no ground pin so I must be missing something obvious, right?

[1] http://www.cpu-galerie.de/html/intel8008-m8008.html

It's a bit tricky. From the 8008's perspective, it's running on -14 volts. But the 8008's Vcc (i.e ground) is connected to +5V, and the Vdd is connected to -9V. So when the 8008 outputs a 1 (high), the output is +5V (more or less), which is TTL-compatible. When the 8008 outputs a 0 (low), the output will be negative. Apparently, TTL is fine with negative input voltages, so this is acceptable.

The point is by shifting the 8008's supply to +5V/-9V and ignoring ground, the outputs automatically work with TTL.

Due to the threshold voltage, the low will be quite close to 0V. A TTL input is the emitter of a transistor, so trying to pull it slightly negative won't do any harm; and if anything, may actually help the transition be a bit sharper:

https://en.wikipedia.org/wiki/Transistor%E2%80%93transistor_...

I'm a little slow today. There was an article about a month ago on the Sac State 8008 and it had a link to the user manual which contained a high level schematic of that computer. Sync goes straight into a TTL inverter. So ya, TTL, of 1972 vintage anyway, didn't seem to mind -9V as an input.

https://news.ycombinator.com/item?id=24515156

Figure 10 shows how the interfacing of that machine worked. http://www.digibarn.com/stories/bill-pentz-story/docs/8008UM...

Interesting, I thought TTL didn’t like voltages that were too negative but I’m definitely not too great on the historical stuff.

This data sheet for 7400 logic, which admittedly only goes back to 1983, doesn’t like inputs below -1.5V

That could very likely be because ESD protection was added and 1970 TTL parts didn’t have that.

https://www.jameco.com/jameco/products/prodds/910901.pdf

You can grab a copy of the 8008 User Manual here:

https://www.manualslib.com/manual/943056/Intel-8008.html

The 'download' link works, after possibly answering a google image captcha.

On pdf page 2 the "features" says the I/O lines are TTL compatible.

On pdf page 15 begins the "electrical specifications" section, and it looks like they just pull the outputs down against Vdd with a MOS transistor (see "Output Buffer" diagram in figure 7).

Thanks! The pin out on page 2 has no ground, so what are they pulling down to? That’s my question. I can imagine a couple of ways to do make the TTL levels so I’m curious which way it was actually done.

According to the diagram of the output buffer on pdf page 15, they pull down against Vdd (the negative supply). What is left unstated is that the pulldown transistor has likely been designed with a Vt such that when "on", and pulling down against Vdd, the output goes quite close to zero volts.

It just dawned on me that you could use the Vol=Vdd-Vt property of the inverter to level shift up the IO output closer to ground. Especially if one did a circuit that did Vol=Vdd-2Vt one could get a low output that’s pretty close to ground. Is that what they did?

The output pins are pulled to Vdd (-9) by a transistor driven by a bootstrap load circuit. So you'll lose one threshold voltage, not two. (You can see these bootstrap load capacitors in the die photo near the pads.)

Inconveniently, the 8008 datasheet doesn't specify how low the low outputs are; it just says they are at most 0.4 volts.

Thanks for the information. It so cool that you can just examine the die and know the answer.

There are definitely trade offs to consider so I can understand why the Intel engineers took that route.

On the one hand, one gets a very negative output level, which I suppose no one really cares about in the 70s so maybe that’s not even a disadvantage. But to level shift more toward ground would consume more die area per IO and increase the output impedance of the pin, unless one did another buffer stage, which would be even more die area.

It’s interesting how we can just absorb this extra complexity in modern circuits without even batting an eye. It’s barely even considered as extra complexity.

In "The diagram below shows the bootstrap load circuit.", you use Q1/Q2/Q3 designations but these aren't labeled in the diagram.

Also can you explain a little more about the "load resistor (which is actually a transistor)"? It looks like this is actually a current sink or something?

Thanks for letting me know! I've updated the diagram with the right version.

Yes, the transistor is a current sink. Since the gate is wired to Vdd, the transistor is stuck on so it provides a fixed current limited by its size. Transistors are much smaller than resistors on an IC so they used transistors instead of resistors.

> Yes, the transistor is a current sink. Since the gate is wired to Vdd, the transistor is stuck on so it provides a fixed current limited by its size.

That seems wrong? Q3 appears to be effectively acting as a diode with cathode fixed at -9V and a 5V threshold, such that Q2's gate (Q3's anode) can never be above -4V, but will be pulled lower by the capacitor if `out` drops. (At which point Q3 doesn't provide any current because its anode is down at -18V.)

I was answering the question about the load transistor in the earlier inverter diagram, not Q3. I mention Q3's diode action in footnote 5.

Ah. That makes sense, then.

Ken, thanks for yet-another amazing and dense article.

Somewhat off topic, but you have written about four-phase logic and AL1 in particular (eg. http://www.righto.com/2015/05/the-texas-instruments-tmx-1795...) but I have yet to see a similar deep treatment of it. How did the technology compare and why didn't it get more attention?

I have a Four Phase chip that I'll write about at some point. (Not the AL1 arithmetic/logic chip, but an I/O chip.) I think the main reason that Four Phase's AL1 didn't get more attention is that the processor was used as part of a proprietary computer, so it didn't have much visibility. In comparison, the 8008 was sold as an individual product with extensive documentation and support (essentially creating the microcomputer industry). The other factor is that improvements in NMOS made four-phase logic the losing technology, so it was mostly forgotten.

Thanks, that makes sense. Maybe I should have asked differently: at the time of its introduction, it seemed like four phase logic (the technology) ought to have had superior absolute performance and even performance/area. It seems like a static version of Intrinsity's Fast14.

EDIT: clarified that "it" is the logic approach, not the end product.

My impression is that in 1967 four phase logic was the superior approach, but by the 1970s technology had changed enough that it wasn't. The problem is how to implement the pull-up on your gates. The four phase approach precharged the gates using 4 different clock phases. This was fairly efficient since you just wasted one charge. In contrast, using a pull-up transistor meant that you had a constant current flow, wasting power. The disadvantage with four phase logic is that each gate level takes two clock cycles. If you use static logic, on the other hand, you have the propagation delay through the gates. Another disadvantage of four-phase logic was the more complex design. I think it also required one more transistor per gate.

The main technology changes between 1967 and 1975 were the switch to silicon-gate transistors, the switch from PMOS to NMOS, and the use of depletion-load transistors. I think these considerably reduced the advantage of four-phase logic. The common microprocessors of that era (8080, 6502, Z-80, etc) used depletion-load NMOS logic, although the IMP-16 and TI TMS9900 apparently used four-phase logic. I'm currently looking at the Mostek 4116 memory chip which uses weird precharge logic, probably not four-phase, but I haven't figured out yet what's going on there.

I've read some of the papers on four-phase logic, but haven't studied it closely enough to be sure of the above. So I welcome corrections and more information about the demise of four-phase logic.

Thanks for going to such lengths to share your joy with us.

Amazing stuff, as always.

Very interesting. Some now-obsolete audio power amplifier IC's used a bootstrap method to increase output swing. But I never imagined it being used in a microprocessor!

It's also very common in switching power supplies as it allows N-type devices to be used in the high side improving efficiency for "high" output current supplies. Here is an excellent summary of the various techniques.

https://www.onsemi.com/pub/Collateral/AN-6076.pdf.pdf

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