Comment by pjbk | Hacker News Reader

Comment by pjbk | Hacker News Reader

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Totally agree.

Being involved with FPGAs for 20+ years now, and Xilinx for the most part of it, I have witnessed the progressive decay of their software quality. The legacy Xilinx tools (Foundation) were far from perfect but at least useable -- and hackable to a degree if you needed to implement workarounds. Those were many times even suggested by Xilinx own employees that were easy to approach and responsive back in the days.

Altera Quartus was always better in terms of project organization and user interface, including their hardware tools. Third party software such as Synplify (before Synopsys bought their maker Synplicity) were light-years ahead, especially on the synthesis introspection and support for design and RTL troubleshooting.

People tend to justify the software quality and vendor lock-in because these are niche markets. I think that is a lame statement. You could tell both Xilinx and Altera, being "fabless hardware companies", treated their software departments as a necessary burden and not a critical part of their business model, which by de facto it was. The software started going downhill, progressively accumulating technical debt while it kept getting even more cryptic and expensive. I think they offshored a significant part of its maintenance in the last decade. Each release fixed bugs but astonishingly introduced very stupid new ones that a minimally decent software verification process should have caught.

Vivado is a mess. You can optimize your workflow digging down deeply with TCL scripts (yikes, its 2020!). However who has the time for learning their badly designed API and fighting with the quirkiness of their tools? I am amazed some of us use it in regulated environments where our tools need to be properly validated. I have had designs that take more than one day to synthesize, map and route. Having being bitten by some bugs and my own errors dealing with the cumbersome IDE, I always painfully go through all the logs of each step, and also many times recreate the project and rebuild just to check if the output is reproducible.

> Vivado is a mess.

I recently encountered a bug in the Vivado IP integrator packaging whatever crap where if you left the "Vendor name" field at its default value '(none)', the packaging aborted with an error because that field contained invalid characters: the parentheses. That's a bug that any kind of testing should have caught (two bugs, actually).

Also: Why does Vivado have to treat any little IP core I create like it's some full-fledged library that exists independently of my main project? I just want to attach a 50-line HDL module to an AXI interconnect in the block diagram – I don't want to create a new project for this, ffs.

Vivado is amazing. TCL is chosen because its portable across almost All EDA tools, so by using it, Xilinx are ensuring your existing HW design skills apply to FPGA tools also, instead of the proprietary interfaces ISE used. So while TCL is not a language I like, it is the HW standard so it must be in any serious EDA tool. I use many EDA tools daily (design compiler, primetime, icc2, vcs, xcelium, verdi, redhawk, and vivado) all have TCL, so some scripts are portable between tools, which is I assume why Xilinx chose to also have some command compatability with the Synopsys commands. So doing this makes HW design skills portable, which I really appreciate. This was also why they moved to XDC constraints from the UCF, embraching existing standards to help engineers.

I'm not sure about amazing (there's certainly worse FPGA tools though), but I think you're right on TCL. It's still a perfectly servicable language to do the job and it's ubiquitous in the industry so you'd need a pretty strong reason to break from it. The terribleness of the tooling comes from other sources (mainly its sheer opaqueness, followed by bugginess, followed and excacerbated by its slowness, though the last point may be hard to get around: place-and-route is not like compiler optimisation, compiler optimisation is almost entirely local decisions, wheras place and route is essentially a global optimisation problem).

I guess my perspective comes from the other side, ASIC tools that do the same thing (synthesis, place and route, STA, simulation) are way, way worse. Design compiler was designed in the 90s, and while it has many advanced features, it's usability is incredibly poor. A million variables you never heard of, and each one tweaks its behaviour in weird and wonderful ways, and a GUI that still looks like its from the 90s. Costs 90k a seat to boot, but if you're doing ASIC design, it's one of the major tools you will use. And it just does the synthesis bit. Vivado does it all, and has seamless cross probing between each stage, right back to source code. It's usability to me is refreshing. I have found bugs, sure, but never a show stopper. It's free Verilog simulator (xsim) is better than any other free system Verilog simulator out there, and that's just one sub component of Vivado.

oh yeah, by all accounts ASIC design tools are even worse. But from a software perspective FPGA tooling is still in the dark ages from most perspectives (and the frustrating thing is a lot of it wouldn't be very hard to do better).

I just wanted to let you know that I’m going to print out a poster that says “TCL scripts (yikes, it’s 2020!)” with the Xilinx logo for our office...

You can always tell when someone is a seasoned FPGA veteran by the quality of their rants about the tools.

Tcl is the de facto scripting standard for EDA (it's in thr name!), it's a quirky language, but what Xilinx has done is allow portability and compatability between it and major HW design tools. The low levels commands themselves are similar to ones ASIC designers would use, e.g. report_timing is the same as you would see in countless other EDA tools. Perhaps supporting python and TCL for scripting would be good, but not supprting TCL would have been a big mistake

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