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Comment by adrian_b | Hacker News Reader

The new Zen 3 cores are expected to have a higher AVX throughput per cycle than all Intel CPUs, except the most expensive models of Xeon Gold, Platinum or W and the HEDT i9 models that have dual AVX-512 FMA units.

The cheaper models with only one AVX-512 FMA unit have a lower throughput, which will be exceeded by Zen 3, even at the same clock frequency.

For multi-threaded tasks, Zen 3 CPUs will have a higher clock-frequency than any Intel CPU, so it is expected that any older Intel CPU will be beaten easily.

It remains to be seen which will be the performances of the Ice Lake Server CPUs, to be launched before the end of the year. However, miracles are not expected, because these are using the older Intel 10 nm technology, not the improved one used by Tiger Lake.

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> The cheaper models with only one AVX-512 FMA unit have a lower throughput, which will be exceeded by Zen 3, even at the same clock frequency.

I think there are relatively few with only one FMA (and there's no way of interrogating them at runtime, sigh) but, yes, if you know you have one, you use AVX2 for GEMM kernels, as a specific example.

For general computational workloads, you're likely better off with more AVX2 cores and high memory bandwidth, even without whatever improvements there are in Zen 3.

> and there's no way of interrogating them at runtime, sigh

Well, directly, no.

Indirectly ... find the model and use a lookup table to find how many FMA units it has :P

I've been through the exercise. It's obviously tedious and fragile, and not always possible, as far as I remember. I can't give an example of something that wasn't listed, but I at least have queries against D series and i7/i9.

Most or all workstation CPUs with AVX-512 (Xeon W or Core i9) have indeed dual 512-bit FMA units.

However most server models with AVX-512 have only one 512-bit FMA unit. That includes all Xeon Bronze, all Xeon Silver and a few Xeon Gold.

All Xeon Platinum and most Xeon Gold have dual units, but those are extremely expensive.

Fair enough. I've just never come across 1 FMA versions, despite trying to enumerate them -- doubtless computational bias.

I've ordered a tiger lake laptop which should arrive around the end of the month, so I'll be able to test then. So just speculation for now:

I'd think AVX512 would still be advantageous for gemm kernels. If you use a 16 x 14 microkernel instead of an 8 x 6 microkernel, you'll reduce memory bandwidth by halving the passes over the cache-sized blocks in memory. Well optimized implementations don't really have a problem with this (getting close to the CPU's peak flops on AVX2), but it still seems better than not doing it, and is an advantage for code with register tiling more generally.

I suspect that it'd help people using Tullio.jl in Julia, for example.

Yes, even on a computer where the throughput of AVX-512 is the same as the throughput of AVX/AVX2, like Tiger Lake, it is usually much easier to reach that throughput with AVX-512 than with AVX/AVX2.

The mask registers can eliminate special prologue or epilogue code for the loops and having more and larger registers make it much easier to overlap enough computations so that the latencies of the operations are hidden.

I would never buy again an Intel CPU without AVX-512, because that has already for some time been their main advantage and now it remains their only advantage over AMD.

Unfortunately for Intel, even if AVX-512 is a great improvement, it cannot compensate for a number of cores half of the competition. Intel needs to launch the 8-core Tiger Lake H no later than March 2021, but it would be better for them if they could do it earlier.

> it is usually much easier to reach that throughput with AVX-512 than with AVX/AVX2

That's not what I understood from people who've gone through the exercise for GEMM. One probably relevant measurement: on BLIS' generic C GEMM micro-kernel, GCC doesn't get nearly as close to the hand-coded avx512 version as for avx2 with appropriate bock sizes.

Yes, if you have two AVX512 FMA units, you use them for GEMM; with a current microarchitecture implementation, if you only have one, you don't. https://github.com/flame/blis/blob/2d8ec164e7ae4f0c461c27309... GEMM is one of relatively few computations with sufficient computational intensity.

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