There are a number of full-3D designs in the works today. The challenge has been thermal dissipation, and as long as it's not logic-on-logic, it works. So that becomes a placement challenge, and EDA tools are still catching up. But there are some interesting new approaches out there, too. TSMC has figured out a way to stack chiplets inside a chip. So rather than going up, it's going down. They say that approach solves the thermal issues because the silicon acts as a heat sink. Here's a story that explains it: https://semiengineering.com/momentum-builds-for-advanced-pac... (Scroll down to the SoIC stuff under TSMC). The front-end packaging is new, meaning it's done at the front end of the manufacturing process. More work is being done the traditional way, too, whether it's pillars rising up off a substrate, or die on die (or die on die on die).