TSMC’s Wafer Prices Revealed: 300mm Wafer at 5nm Is Nearly $17,000 | Hacker News Reader

TSMC’s Wafer Prices Revealed: 300mm Wafer at 5nm Is Nearly $17,000

tomshardware.com

104 pointsrbanffy85 comments

Anandtech should have an article with primary source instead of this estimate. ( Assuming they are allow to publish it )

1. It is no use discussing yield % without putting the die size. It is defect density per cm2 that is the most important factor. ( Your yield percentage change due to design and die size )

2. 5nm defect density is better than 7nm comparing them in the same stage of development. i.e Very Good.

3. TSMC is actually open and transparent with their progress and metrics. Both in Investor Meetings and Technical Forum. ( And with their business partners.... something most other Foundry aren't doing as well )

4. Most of these calculations in the comment are in BOM cost, which completely ignores the Design Cost ( Billion ) and Research Cost, in terms of Apple that is Architecture Cost, and IP Cost such IMG, FPGA ( Lattice ) etc that are paid per unit. ( Edit: And testing, packaging cost, but it is relatively small )

5. Hopefully with these figures in mind, you will see how Qualcomm is fighting hard to compete, considering they will have to sell it with at least 50% margin. ( And why Nvidia dont necessarily want to be in the Mobile SoC market, as suggested in the ARM- Nivdia discussions previously )

6. And then you should realise, how the ARM royalty portion is not an important cost factor. ( As per all ARM or RISC-V discussion on HN )

7. You should also notice the trend of Wafer Pricing. Hopefully that will finally shape your view on Moore's law.

>ARM royalty portion is not an important cost factor

That's exactly the reason why Nvidia's pending acquisition of ARM is so suspect. There's not much money to be made in ARM's business model hence it really only makes sense if they plan on exploiting the synergy of ARM + Nvidia tech in a way that only ownership of the company allows them to.

No, an option to hike royalties is very much on the table given ARM's very liberal fees by industry standards.

High volume, high margin fat lambs like Qualcomm merrily eating grass around, or obscenely high margin high-end network chips would've ended on a dinner plate much, much earlier if ARM had an American business culture.

Softbank can do that themselves if that was the plan.

SoftBank needs cash now, not later. Their horrible bets all got called this year.

Softbank is getting just $2bn right now. And the next payment at closing is only $10bn, the rest is in stock.

The whole Softbank needs cash now to fill the WeWork hole doesn't add up. They could have made more cash with an IPO, in similar timescales.

Just doing some napkin math to give myself some other context in my own head with something much smaller, die size for the Apple A14 isn't out yet, but the A13 (found in the iPhone 11 series and SE 2) is around 98mm^2 manufactured on TSMC's 2nd gen 7nm N7P. A14 might be something like that, because while it's a smaller process Apple boosted transistor count by 38% as well. Lazily/conservatively taking off 10mm on the edge for squares into a circle, that'd be about 630 chips per N5 wafer, a high enough count that chip loss rate shouldn't be too far from defect rate. Even assuming they can get 90% yield right out the gate (maybe generous) that's still about $30/chip, just for manufacturing without any R&D amortization, packaging etc. That actually seems not insignificant going by historical iPhone BOMs [1], so even for smartphones with their far far smaller SoCs 5nm at launch isn't nothing.

The continued ongoing progress in silicon is just mindblowing when you dig into the details in any real way. I was blown away already watching the "Indistinguishable From Magic: Manufacturing Modern Computer Chips" [2] presentation years ago, which still seems incredible and yet that's all talking about now ancient tech. The increasing costs and design challenges though are also going to have interesting effects on the industry, as who/what has the margins to afford fabbing aggressive chips on the cutting edge might start to diverge a bit more. I also wonder how longevity will be, I remember speculation that smaller processes would eventually have to deal with more risk of earlier breakdown even in more normal shielded settings. And speaking of that, in higher rad environments it's normal to use older bigger processes since they're more resistant to disruption. I wonder if small enough processes ever make that more of a consideration even at sea level.

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1: iPhone Xs Max for example: https://technology.informa.com/606680/iphone-xs-max-costs-ap...

2: https://www.youtube.com/watch?v=NGFhc8R_uO4 (highly recommended if you haven't seen it)

> Even assuming they can get 90% yield right out the gate (maybe generous)

That seems outrageously generous. Rememember that Apple doesn't (as least hasn't so far) bin their parts to sell the ones with faults via different configurations. The only way to get a chip yield like that for a single device configuration is with a ton of redundancy.

I certainly don't know what the yield rate is of Apple silicon, but I definitely don't believe 90%.

>That seems outrageously generous.

Probably, but until we actually get some A14 die shots I don't know how aggressive Apple has been with caches and the like with some redundancy that can be fused off for yield. Again though all the numbers are napkin math and trying to give some fudge factor in both directions, so conservative on the number of chips total (I didn't try to calculate exactly how many full squares fit I just took off an entire outer radius) and generous on the yield. Mainly I was trying to reason about the question of "even if everything goes great, and even if it's something smaller not a monster desktop GPU or the like, is it still a non-trivial cost?" to which it seems like the answer is yes. If it's actually a smaller yield that just makes it get even more expensive, but yield itself won't be a silver bullet.

Usual yields are quoted at 60-75%. More for smaller chips. But can you even tell how many cores are actually running in your iPad? Maybe they do fuse out a faulty one.

On modern chips, we are not only "fusing out" faulty cores. We also put more memory cuts than necessary into the silicon and we fuse out the defective ones to increase the yield. You can look at Memory BISR (built-in-self-repair).

If Apple wanted to bin the chips, they have devices crying out for low-power draw, albiet slower clock. They can sell a tonne of earphones, watches, HDMI enabled USB-C dongles. They could re-purpose chips which can clock 10x slower for 1/2 the cores, and still have too much CPU. But free.

They can use them for the Apple touchpad, the keyboard, the on-mobo controllers which currently consume non-general-purpose chips, if they want to. If they displace a 10c part by an otherwise redundant $30 part, they are still ahead, if it works.

The power draw for a full blown chip like A13 is vastly different from that of the typical ones you find in the devices you mentioned. Also the form factor could limit for many of the smaller devices

Yes, I realised this was stretching the argument after I posted. Probably, repurposing terminates in slower, lower spec devices the A13 targets anyway. Maybe in something like the Apple TV?

It would be true that compared to Intel they have far less binning opportunities

One way to bin it would be:

Macbook -> iPad -> iPhone -> Apple TV

Not sure if they still are, but for a while they were shipping Apple TV's with Apple CPUs which had half the number of working cores, but they were running it with higher thermal limits.

> If they displace a 10c part by an otherwise redundant $30 part, they are still ahead, if it works.

I am no expert, but my intuition says that even die size alone would present a problem.

Are Non-Pro iPhone and cheaper iPad not using slower clocked chip?

> And speaking of that, in higher rad environments it's normal to use older bigger processes since they're more resistant to disruption.

This was mostly debunked in https://news.ycombinator.com/item?id=24430234 with some nuance.

That's quite cheap.

Consider how gigantic a wafer is.

I can of course only run calculations against the half price 7nm node but you will see...Even the mammoth (as in, reticle limited) nVidia A100 is just 826mm^2. https://anysilicon.com/die-per-wafer-formula-free-calculator... says 57 of those fit on a single wafer. This table says the price of a 7nm wafer was 9346 so nVidia paid about 164 USD for each of those. The A100 card -- of course piled with RAM but still -- sells for ten grand.

That's double the rumored price of 7nm wafer and 5 times of 14nm wafer

~650MTr per $ at super low power level, not bad.

TSMC's N5 process density is ~171MTr/mm2 and the area of a 300mm wafer is 70,685mm2. Shave off maybe 5,000mm2 for edges and you're at 65,000*171,000,000 = 11 trillion transistors for $17k, or about 650 million transistors per dollar. Apple's A14 11.8BTr so minimum ~$18.20 at this price. Of course there's defect rate to consider.

Bah, I could setup a large format camera and do optical reduction of an arbitrary B&W image, transfer that image onto a semi-conductor with a laser, then deposit a thin layers of metal (and whatever) onto it in a vacuum chamber for like, maybe $5 of material. What a ripoff.

You can in fact do this.

The process for the original 6502 chip is publicly available I think. You could make it even smaller than the original 8um, probably.

I know its possible, I was only being 25% facetious (which is presumably why someone downvoted me). FWIW in all seriousness, getting anything non-trivial to work at 8um would be VERY impressive in a garage-level environment, and of course you'd still be off world-class fabs by 3 OOM!

Then go show the leading world manufacturer how it’s done by opening your own fab and turning out billions of chips. Even with 100,000% markup from your $5 cost basis, you’ll have customers lined up for the next decade if you could really pull it off.

We won’t hold our breath waiting to hear back on your success... ;)

Pretty sure they were joking!

Pretty sure I was too!

For some context, the table is on pages 44 and 45 of this PDF: https://cset.georgetown.edu/wp-content/uploads/AI-Chips%E2%8...

via https://twitter.com/chiakokhua/status/1306437988801486848 (the article is based on this guy's tweet)

Also note these are not actual prices but estimates.

I wonder what the internal cost is for TSMC to do a wafer is?

The variable cost if you will: The cost of materials, electricity, staff etc.? Probably a very small amount.

The big cost for TSMC is the fixed cost of the expensive equipment and the massive R&D in developing the process. However the amount is interesting since if you wanted to spend a massive billions of dollars and setup a competitor to TSMC, you know that TSMC would be able to compete with you on price all the way down to that point.

You can look at ratios like WACC and ROIC.

TSMC's weighted average cost of capital is 7% (WACC)

ROIC % measures how well a company generates cash flow relative to the capital it has invested in its business. For TSMC the ROIC is 28%.

If you would like to compare competitors these ratio's combined with growth rate give a very good market overview.

https://www.gurufocus.com/term/wacc/NYSE:TSM/WACC-/Taiwan-Se...

>The variable cost if you will: The cost of materials, electricity, staff etc.? Probably a very small amount.

You will actually be surprised electricity is an important cost factor along with Materials in COGS.

That 5nm process is the world's smallest, which means that the variable costs include a) purchasing the purest of pure materials and b) working on them in the cleanest of clean rooms. Neither sounds cheap to me.

In the table on the page, why does "Foundry sale price per chip" decrease, while "Foundry sale price per wafer" increase?

Does it have something to do with the average chip area being much larger at larger process nodes?

Area, intrinsic process cost, and also TSMC is a monopoly at the leading-edge node. They can charge what they wish.

Isn’t it normalized to a 610nm die on all processes?

That only explains costs not prices

I assume as transistor density increases, you get more chips per wafer.

AMD style chiplets also increase yield.

> In the table on the page, why does "Foundry sale price per chip" decrease, while "Foundry sale price per wafer" increase

I had the same question. Seems it's based on an earlier table in the same PDF (see my top-level comment for source link), namely Table 7 on page 41, which lists transistor density to calculate average chips per wafer.

And then, for the table referenced in the article (which is Table 9 in the PDF), it says: "In line 8, we convert the per wafer value to a per chip value by dividing by the number of chips per wafer of a given year’s node listed in Table 7."

Line 8 of Table 9 is misleading out of context. If you dig into the report itself, it's calculated based on a hypothetical chip with the same number of transistors for each process (Table 7). For example, the 90nm process is listed as yielding "0.7" chips per wafer, which is obviously nonsensical. Line 8 would be more appropriately described as "cost per 90.7 billion transistors", if I am reading the report right.

For info, around 600 A13 chips fit on a 300mm wafer. Means Apple is paying around $29 per chip.

A13 is 98.5mm2 & 8.5BTr, so ~86MTr/mm2 density, a bit lower than what chart estimates [1] (95MTr/mm2 for 7nm).

A14 might be a significantly smaller chip since its 11.8BTr / 171MTr/mm2 (chart estimate) = ~69mm2 size

[1] https://en.wikichip.org/wiki/5_nm_lithography_process

If the chip yield is 100%.

Apple may be paying just for working chips, rather than wafers.

If you're their largest customer, and there are no alternative suppliers, leverage works both ways -- but it's beside the point. TSMC does multi-year low-scale runs of new processes to figure out tooling and reduce errors, before committing to huge orders.

That's a pretty good price. Imagine if masks did not cost so much to make. We would see tons more custom designs.

How do defects factor into pricing? Do you pay $17,000 per wafer, regardless of the amount of defects? What if TSMC's estimates are off? If defects are higher than expected, do you get a rebate?

You pay the same per wafer regardless or defects.

I'm assuming whatever happens if estimates are off is a crapshoot depending on your contract and specifics.

I could be wrong but there is also usually at least a little 'buyer beware' on newer processes; I know that was a big part of AMD being kneecapped at the offset of the Bulldozer arch era.

The title should say Estimated, not revealed.

I'm surprised, that's pretty cheap

I assume it's bulk prices, requiring thousands/tens of thousands of wafers of commitment.

The smallest practical commitment would probably be 25 wafers. Any fewer and you would be wasting useful capacity.

I don’t think they need to require it - you’d be crazy otherwise because you have to pay the multimillion dollar cover charge (to make the masks).

Paying for the masks is the big upfront cost - into the $5 to $10s of millions depending on the process node.

Someone told me around $30 million for a 14 layer chip in TSMC 5nm but I couldn't get real confirmation.

No one who really knows can say due to NDAs. We just know rough order of magnitude price.

I can see $30 million for 5nm. With material costs approaching $20 to $30 a chip for mobile SoCs, you need quite a high sales price and volume for the economics to work.

14 layers is a suspiciously small number for 5nm.

It will be a big surprise if multiple patterning elimination can reduce the layer count so dramatically.

14 metal layers.

Can someone help me contextualize? 300mm diameter is 70,686 mm^3. If a chip is 300mm^3, does that mean the company can print about 235 chips per wafer or is it much lower? At 235 chips and a 100 dollar retail price, that doesn't leave much of a profit margin (23,500 gross vs 17,000 to TSMC).

A 300mm2 chip would have about 50B transistors, 4x an A14 and 1.8x a Geforce GA102 (RTX 3090 chip). Don't think anyone would sell that for $100 in 2020.

You need to check your sources or your math, likely both.

A 5nm 300mm die is pretty close to 50B transistors. The whole chart is based on a 90B transistor 610mm die at 5nm that costs around $200. Hence why the die cost of 90nm implies wafer scale level of transistors for the per chip cost.

They have a lot of NRE and packaging costs to recoup. And room for a decent profit margin if you won wafers (the companies all bid against eachother, not just in price but in volume too to get foundary time).

That's price, not cost. TSMC charges 17.5k, we don't know how much it costs them to make one wafer, probably a lot less.

For context, a skim of random internet sources claim that TSMC produced 1.1M 7nm wafers last year.

Wait, wait. Is this the total price? I think it's much expensive. $17000 for 300mm wafer is unbelievable.

What's TSMC's secret sauce compared to American fabs?

Cheap labour?

Government handouts?

Management incompetence. Too many non-technicals running Intel and GlobalFoundries the past decade.

They got EUV working in production.

Surely America can churn out good Semiconductor physicists?

Dat "Murica!" pride. "TSMC is ahead, is it handouts?" (Hint, Boeing also gets a shitton of handouts, hmm, and they built planes that actively overrode the pilots, and actively wanted to crash instead of fly.)

Maybe if education wasn't so neglected that teachers have to use their own money to buy supplies, and creationism is taught as a valid theory, and instead maths and science are improved by a shitton, then you can churn those semiconductor physicists.

So, who's going to plant their flags on this comment?

Could it? Yes. Is studying to become such a profession something valued by the culture at large? Not really.

STEM generally in America is seen as something for dweebs and nerds to do. At least within the last two decades the really smart math types have been busying with legalized gambling on the stockmarket. A comparison of salaries, free time and quality of life after work, and other life metrics would probably lead many to consider other fields of work.

They all get paid more to develop web frameworks though.

Better work ethic + lower hubris in the work force. American fabs source heavily from a pool of people with a background in the US military. The intent is that it yields a certain caliber (positive connotation) of worker. What they get is the ego of the American male whose path after high school was to join the military. Now actually send that person through the meat grinder, thus ratcheting up their tolerance for bureaucratic incompetence of the sort highlighted in Catch-22, then consider that the US military's infinite budget means that the cost of anything is never experienced in a direct, visceral way, et voila.

> American fabs source heavily from a pool of people with a background in the US military.

I wonder what historical factors contributed to that tendency? What are the forces against starting a new business in this space -- it must be an enormous undertaking to build the production facility?

Probably in the tens of billions plus a decade to get something advanced working. You can do older nodes yes, and there is plenty of business there but your competitors have already amortized those costs and have business relationships built already.

There aren't really subsidies for TSMC here in Taiwan. I would say labor cost is relatively cheap (compared to western countries), and security is relatively high (compared to the Chinese ecosystem).

A big reason it happened here is probably more to do with how manufacturers started combating intellectual property theft decades ago. Firms who wanted to manufacture in China manufactured a few key components in Taiwan to maintain control over output, then shipped them to Guangzhou for final assembly.

I'm not sure there's a "secret sauce". It's more they quietly built a decade plus lead on their closest competitors when they were in the "less desirable market" (compared to Intel, AMD, and Nvidia), and there are huge barriers to entry, with little short-term incentive to DIY (vs. contract manufacturing).

TSMC is actually now Taiwan's single biggest energy consumer, using about 5% of the entire country's electrical supply.

> There aren't really subsidies for TSMC here in Taiwan.

Subsidies don't need to be direct cash handouts/tax deductions. I think the real advantage TSMC gets over its non-Asian competitors is government spending on infrastructure specifically for silicon fabrication. TSMC has guaranteed access to water, electricity and engineering talent from local universities on a resource constrained island.

It's smart industrial policy that is the key behind the rise of a lot of Asian tigers, and something other countries should study as well - laissez faire is not always the optimal answer to innovation.

TSMC is just better right now, better management, better culture, better engineers.

>What's TSMC's secret sauce compared to American fabs?

I have seen this being asked so many times but it still irritate me a lot.

TSMC's secret sauce is the wrong question to ask. You need to ask why GF and most importantly Intel are ( Fill in any or all negative words you may like ).

And that is about as polite as I could have put it.

Not just one secret sauce, but as it is usually the case, a mixture of many things: concentrated long term investment, available talent and infrastructure, geopolitics, hability to make strong business networks, etc...

If you force me to pick one to be the secret sauce though, I would risk to pick their business model. TSMC was a key element in the rise of the fabless value chain, while other fab powerhouses were more vertically integrated. The engineers in my circle who have done designs with their processes usually say good things about the experience.

Imagine how many rtx 3080s could come out of that.

Zero. They are using Samsung 8nm process for producing all RTX 3 series

About 7.

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