[EDIT] See also: https://electronics.stackexchange.com/questions/445323/can-y...
One unexpected thing I noticed in the chip is a control signal to pull lines low during startup. CMOS doesn't like floating signals (since you can end up with the pull-up and pull-down transistors both on). But before the configuration is loaded, the routing lines may not be connected to anything. So the FPGA has to pull these lines low until everything is configured, and then release them.
Newer parts (Spartan-3 and later, maybe even earlier) dropped that feature -- it's no longer possible to create internal bus contention. You can still cause issues by driving an external pin that conflicts with an external driver, but that's pretty standard; even microcontrollers have that issue.