L3 cache is under the "Coherent Fabric" block (it's the 12MB Last Level Cache thing).
https://images.anandtech.com/doci/16063/474551355-Intel-Blue...
I don't see any coherent fabric blocks — what looks like large cache sections to my eyes are entirely inside the "Core" blocks. Maybe they're just not drawn correctly. Here are some much older i7s, for example:
https://www.cs.uaf.edu/2009/fall/cs441/proj1/russell/images/...
https://www.notebookcheck.net/fileadmin/_migrated/pics/Core_...
Right, that was really my main question: besides the labeling (which is of course approximate), the positioning sure looks like each core would have its own "favorite" section of the cache. And being shared, it seems like this could make for some interesting performance behaviors.
Ah, interesting, this topology was introduced with Sandy Bridge. I'm just out of date: https://www.anandtech.com/show/3922/intels-sandy-bridge-arch...
https://cdn.wccftech.com/wp-content/uploads/2020/08/Intel-Ti...
Looks like ya, the L3 cache is "inside" the core blocks.