Hacker News Reader

Comment by en4bz | Hacker News Reader

All this on Samsung 8nm (~61 MT/mm2). They didn't even feel the need to use TSMC 7nm (~100 MT/mm2). Probably keep the price down and to reserve capacity at TSMC for the A100.

This is like the anime hero/villain (depending on your perspective) equivalent of fighting at half power.

View on HN

>They didn't even feel the need to use TSMC 7nm

They just couldn't get enough wafers. They tried to force TSMC to lower the prices and it backfired.

How did it backfire?

I don't have a source on hand, but my understanding is that Samsung significantly undercut TSMC on pricing, likely to stay alive in the high end fab business. Samsung is probably making extremely low margins on these, hence the lower than expected MSRP.

On the slide in the presentation it did say something like Samsung Nvidia Custom 8NM process, so perhaps Nvidia made such significant contributions to the process that it's not really Samsungs process anymore?

TSMC's "customized" 12FFN process just had a larger reticle, so the burden should be on Nvidia to explain any customization. I don't think they deserve any benefit of the doubt here.

Why would Nvidia willingly explain any customization? Surely keeping that secret is a competitive advantage.

Yeah, impressive for the node. TSMC's latest N5 process is 173 MT/mm2, which Apple is using now and AMD (probably in N5P form) will start using next year. EUV is really a big step up.

Reply on news.ycombinator.com