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Comment by aclindsa | Hacker News Reader

No - there doesn't have to be. As long as there are no barriers or other instructions which restrict memory ordering relative to particular instructions in the dynamic instruction stream, it doesn't matter what the actual interleaving is between different cores as long as there is a given execution order which is valid for the observable side effects.

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X64 has stronger guarantees than that without barriers doesn't it?

x86 guarants that memory writes to different locations are seen in order by other cores.

If you write memory first to address A and then to B. Another core never can see the B change without also seeing the A change at any moment in time.

But in this case there is only a single memory location. So there is no ordering that could be violated in the first place.

Yes, quite a bit stronger.

In guarantees the order of visibility of writes to shared locations. It dose not guarantee the granularity of updates to the shared locations, which is the essential difference here. How do you observe the difference between the three instructions just naturally happening to all run before your next instruction completes, and them eliding the memory operation as is happening in this optimisation?

It's like the ABA problem - how do you differentiate between just never happening to see a B out of chance, and B being elided instead? You can't.

#StoreLoad still requires a barrier even on x86.

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