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Yes, AMD probably added the optimization because it was a common pattern emitted by compilers.

I wonder if this causes a performance penalty on position independent code, which seems to be used a lot on non-Windows platforms [].

[] It always struck me as one of those propeller-head features that GCC & co. love but which the MS and Intel compilers avoid 'just to be on the safe side' :]

He mentions this doesn't work with RIP-relative addressing, but I don't see how it would cause a penalty otherwise.

re your thesis, can't wait for a WASM ISA on a commercial CPU and canvas instructions for its graphics coprocessor

you'll need to wait for WASM to become "the dominant language" on a commercial CPU. definitely not next year.