Once upon a time (the "Dennard Scaling Era") VLSI circuit design used the same relative geometry at different "feature sizes" - all dimensions of the design(wire width, wire spacing, gate length, gate pitch, ..., etc.) scaled by the same amount from generation to generation, so it was possible to completely specify the transistor layout with a single dimension (generally called 'L'), and derive all other measurements from that as a multiple of 'L'. Transistor density was proportional to 1/L^2.

The measurement that was used originally for 'L' was the gate length.

As designs shrunk below 40nm, it became impossible to shrink _every_ dimension proportionally. In particular, for planar silicon, gate length stops shrinking around ~30nm, but other things could still shrink. This meant that transistor density could still increase, but the relative geometry of wires/gates/spacing/etc. had to change, so it was no longer possible to specify the full geometry with a single number.

But people liked the single number as a handy way of comparing processes, so marketing kept using it as a way to compare processes. The way they decided to do that was mostly to try and keep the proportionality between the transistor density of a process and 1/L^2.

To the extent a "feature size" number of a process means anything, it means "the relative transistor density of this process is equivalent to what you would get if you had used the old (>40nm) geometry, and shrunk 'L' to the specified feature size". Even that relationship has degraded in recent years - now it's more like "we calculate the new feature size as the size of the previous process divided by sqrt(2)".

Regardless, as stated in the parent, there is no single dimension of any recent process that corresponds to the '3nm' number.

There's lots of resources online that describe this, but for an overview, you could start here (describes pre- and post-Dennard scaling): http://www.eng.biu.ac.il/temanad/files/2017/02/Lecture-4-Sca...