The Forgotten Ones: HP Nanoprocessor

> I’m curious how they handled ALU specific instructions if an ALU isn’t present. Does the decode stage just convert them to no-ops?

There were no ALU specific instructions. The article brushes across how ALU operations were performed, but leaves the explanation for how to the reader to understand. The ALU would have been an I/O device (likely memory mapped I/O [1]) and ALU operations would have been performed by writing data out to the external ALU, waiting for the ALU gate delay, then reading the results back in from the external ALU (i.e., input/output operations):

> If you needed support for an ALU you could add one externally (likely with a pair of ‘181 series TTL). Even with an external ALU the Nanoprocessor was very fast.

[1] https://en.wikipedia.org/wiki/Memory-mapped_I/O

Just guessing, but it's probably a memory mapped 74181. The 74181 had 12 input pins: 4 bits to select the operation, and 4 bits each for the two inputs. There were 6 pins of output, 4 bits of data, a carry bit and a comparator bit. Perhaps you'd write to memory mapped latches in front of the inputs and then read the output at a different memory mapped location.

The link is dead for me now, but I browsed it earlier, and got the impression it didn’t have instructions for the ALU, but would write data to the input pins of the ALU and read the result back from the output pins somewhat later.

If I interpret appendix C of https://www.hp9845.net/9845/downloads/manuals/Nanoprocessor.... correctly, that hunch is right.

It seems kind of an inelegant solution to me. They could just solder a resistor to the package at the factory or do some variation of that idea.

Now, modern processors are binned, too, depending on the CMOS process corner they turned at. Slow ones have advantages too - leakage is much smaller, so better suited for mobile.

Or, in case of some SoC, if it's FF (fast NMOS, fast PMOS), they can reduce core supply by tens of mV.

There's even a company specialized in PVT (process, voltage, temperature) monitoring for newest SoC's - Moortec.

Arguably the number of transistors scales as the area, so 10002 == 1e6.

Never panned out, they canceled it years ago.

https://www.extremetech.com/extreme/207897-hp-kills-the-mach...

Heard on the grapevine that there was an exclusive IP licence to some company that did nothing with it, as part of HP's chronic mismanagement.

Vaporware from the start. Very hard to find information about now, I suspect it was dropped as a project without any kind of announcement.

HPE took it; killed it.

Can someone explain how this happens?

80 upvotes now on HN. Possibly 400-500 views. How do they go down so fast?

And archive bot manages to get past it.

I don't know how much it traffic it takes to take smaller websites down. Is it this small?