The devil in the details is that when 5V-tolerant I/O are naively configured as such, device reliability drops like a rock. You'll likely find this disclosed in the manual fine print. Something to consider when prototyping a design destined for production.
What's the software requirement side look like? Intel's website[1; under Legacy Devices] says Quartus II v9.0 was the latest release that could target FLEX 10K devices. Doesn't look like you can download that release anymore, and liable to run into compatibility issues just installing on modern OSs without a VM.
Bummer, and a real shame given how seemingly common regressions are in this space. Not my specialization, but anecdotally over a decade or so, I've encountered scenarios on MAX 7000 and Cyclone II (Quartus II v9.0 builds, v10.x breaks), Virtex-7 (Vivado v2018.3 builds, v2019.1 breaks) and Virtex-5 (ISE v14.6 builds, v14.7 breaks).
I assume interfacing simply with cheap ATMEL and PIC MCUs is another use case.
The university boards can also support 3.3v.
http://leadshine.com/ProductSubType.aspx?type=products&categ...
I do wonder what's the best way to translate to 5v and back. There has to be some fast-switching, go-to part for the purpose.
D lines and some signals need to be bidirectional. And I might even need to do bus mastering, so most signals would have to be.
http://marc.retronik.fr/motorola/68K/68000/The_68000_and_its...
And, yeah...you have some work ahead. Lots of bi-directional, tristate, open drain, totem pole/push-pull, etc.
I didn't have that one PDF, so I saved it for safe-keeping with my other 68k stuff. Thanks.