I think that the radius of a Silicon atom is about 0.1 nm. ~1 nm may be the limit of what's possible. The next nodes after 3 nm are likely going to be 2 nm and 1.4 nm.
3 nm is not available yet, though. Current best is 7 nm, I believe.
3 nm is not available yet, though. Current best is 7 nm, I believe.
I'd really like to know if the fab producers repeat some kind of procedure to create smaller chips or if a new prodigy to make breakthrough findings has to be found every other year to adhere to Moore's Law.
It means that, leaving whatever physics considerations aside, the size of structures is limited by the size of the building blocks.
1 nm is about 5 silicon atoms so cannot be physically shrunk much further. I suspect that there are further physics limitations (e.g. you may be an isolation channel to be wide enough to actually isolate by preventing things like tunneling, etc.)
That's why companies like ASML are so critical. The technology to work at these scales and wavelengths is very tricky.
From Wikipedia: "ASML manufactures extreme ultraviolet lithography machines that produce light in the 13.3-13.7 nm wavelength range. A high-energy laser is focused on microscopic droplets of molten tin to produce a plasma, which emits EUV light." (that's UV close to the X-ray range...)
This is a great talk on the history of chip processes: https://www.youtube.com/watch?v=NGFhc8R_uO4
This is about some of the challenges that had to be solved for a current modern process: https://www.youtube.com/watch?v=f0gMdGrVteI
the node names do not represent any actual measurement of the chip anymore, and have not for at least a decade. There is no measurement of a "5nm" chip that measures 5nm, and scaling is in fact largely dominated by how close you can place the transistors, not the actual transistors themselves.