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Comment by swah | Hacker News Reader

I wonder what exactly the FPGA does, and how they can make it practical and flexible. Of course they could always just test with C and then compile that to HDL.

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A month or two ago I spoke to someone working in these shops. Apparently, they're using the FPGAs to run many of the high-bandwidth algorithms, because going from NIC to motherboard to CPU and back again added too much latency. So they program the algorithms into the FPGA (which has its own Ethernet port) so it can receive, process, and send the data without ever hitting circuitry not dedicated to the task.

This seems a bit surprising: what is the latency coming from the NIC to the motherboard ? I somehow doubt the latency due to distance within one piece of hardware matters (current CPU cannot do much more than a few 1000s cycles for the electricity to go around a few times in a motherboard, which is nothing to do any kind of advanced processing).

The problem is that a high-bandwidth link overruns the CPU with thousands of interrupts per second. It can paralyse the system, where the CPU is so busy handling I/O that it doesn't get around to actually scheduling processes.

Disclaimer: I sometimes consult for HFTs but we don't use FPGAs (yet).

So it is more an architecture issue with conventional hardware ? It makes much more sense to me with this explanation - the issue is the same as in most real-time systems then (like in embedded hardware for audio gears, which is more familiar to me than HFT).

Don't things like real time linux or soft real time patches for linux help, though ?

> Don't things like real time linux or soft real time patches for linux help, though ?

I don't see how it could.

The CPU essentially drops everything it's doing when a packet comes in. Have that happen often enough and there won't be time left to do anything else, unless you start dropping packets.

We see this behavior on high pps routers -- but isn't this why you have multiple CPUs and thread-based interrupt handling?

Doesn't interrupt moderation and receive-side scaling (new Intel NICs can even do rule-based queue distribution) sort this out?

It's pretty terrible (in HFT terms), particularly if you're trying to use a junky on-board NIC.

Folks not using FPGAs use separate ethernet cards and enable kernel bypass and can do significantly better with that.

This is true, but FPGAs can still only handle relatively simple algorithms. FPGAs make certain kinds of tasks nearly trivial (think truly parallel tasks such as decoding market data for different instruments), but there's just not enough gates (in most cases) to do interesting stuff in the application / logic layer.

FPGAs canonical use case is still as very fast codecs. There are exceptions, but they're really only the very simplest of arbitrage strategies. And in order to make those work you need top-of-the-line network gear and engineers as well.

But a Virtex 5 could hold several simple CPUs designed for this task ;)

I don't know if the algorithms they use can be expressed easily as state machines though.

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