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Comment by kickopotomus | Hacker News Reader

I think the underlying issue here is that IC design is one or two orders of magnitude more complex than software. In my experience, the bar for entry into actual IC design is generally a masters or PhD in electrical engineering. There is a lot that goes into the design of an IC. Everything from the design itself to simulation, emulation, and validation. Then, depending on just how complex your IC is, you have to also think about integration with firmware and everything that involves as well.

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I don't know that hardware is inherently more complex than software.

The issue I see in hardware is that all complexity is handled manually by humans. Historically there has been very little capacity in EDA tools for the software-like abstraction and reuse which would allow us to handle complexity more gracefully.

Nope this is just not true.

You can crank out correct HDL all day with https://clash-lang.org/, and the layout etc. work that takes that into "real hardware" while not trivial, are less creative optimization problems.

This is a post-hoc rationalization behind the decrepitness of the (esp Western[1]) hardware industry, and the rampant credentialism that arises when the growth of the moribund rent-seekers doesn't create enough new jobs.

[1]: Go to Shenzhen and the old IP theft and FOSS tradition has merged in a funny hybrid that's a lot more agile and interesting than whatever the US companies are up to.

That might be true for analog/mixed signal design, but not for CMOS. The design rules are built into the CAD. The design itself is a immense network of switches.

Not having an advanced degree doesn’t mean you can’t master complexity. It’s the same as with software.

Same issues apply to digital ICs as well. The design is much more than just the rules encoded into the logic. What size node are you targeting? Is there an integrated clock? What frequency? What I/O does the IC have? What are the electrical and thermal specifications for the IC? Does it need to be low Iq? What about the pinout? What package? How do you want to structure the die? There are a lot of factors involved with determining the answers to these questions and they are highly interdependent.

The advanced degree is not meant to teach you how to grok complexity. It's to teach you what problems you can expect to encounter and how to go about solving them.

Signal integrity and analog design start to share a lot of similarity as you start pushing around the edges.

Absolutely. At the bottom, it's all analog!

I suggest you won't learn those things in college. You RTFM and get some experience on real life design projects.

Now, if you are in CMOS process design or responsible for the CAD software itself and its design rules, it helps (a lot!) to be a physicist. For that you need the MS and PhD training.

And the cost for failure is a lot, lot higher... it’s a different model of development because there are many different challenges involved.

Why is it so high if the fab is free? Intrinsic cost of development time and tooling?

Time especially (though costs are also high). Even with infinite budget you still have a cycle time of months between tape-out and silicon in hand.

Ah, you're talking about this as a current-day commercial project. Carry on :-)

I'm a professional PCB designer among other things. Most of what I have learned came from hard-won experience designing PCBs for projects done for myself and my own education even though a custom PCB was hardly cost effective in a commercial sense. They were just much cheaper since my time was free. They weren't useless projects in that what I made was not easy with off the shelf parts, but it would have been possible and there wasn't a timeline to pressure me yet.

But I would not be a professional PCB designer now if it had not been approachable to someone without a budget but with plenty of time and motivation. I've basically spent as much money learning how to make PCBs as other people spend on things like ski trips or going on vacations or other hobbies. A free fab and tools to create designs is a godsend when designing these things is something you want to do for interesting experiments and learning in an otherwise totally inaccessible field. Even if you think now one needs a masters or PhD to do this right, being able to fail cheaply is a pretty amazing learning tool...

That's what this announcement means to me -- free fab means I can finally learn how to do this and get good enough at it that when the time comes that this is a better solution than trying to combine off the shelf functionality I will be well positioned to take advantage of that change.

I am thrilled to release open source designs for cool chip functionality once I'm skilled enough to do it and the only way I'd get there is if the direct cost to me was nothing (even if it's slow).

Yeah, it's a lot more like PCB design, just more extreme in cost and time (especially when looking at debugging and rework). I don't think it's particularly more intrinsically difficult for digital circuits, but it's a lot different from the rapid iteration cycles you have from software (which is the main point). Because of the timescales even for hobbyist stuff you want to invest a lot more in verification of your design before you actually build it. Also the amount of resources available for it is dire, even for FPGAs a hobbyist has a much harder time finding useful information compared to software.

> free fab means I can finally learn how to do this

hate to tell you this, but probably not. there are only 40 slots. those are going to quickly be eaten by people that already know how to do this.

the fab isn't the expensive part anyway. you can get a small run of ASICs done for a few single digit $thousand

If the fab isn't that expensive, all the more reason to learn how to do it proficiently for free, no? Even if it doesn't get produced it seems like a good learning project.

absolutely! but that already existed. (free tools that don't result in something that can be fabbed)

what you would get out of this is access to a google-promoted open source PDK. It's specific to SkyWater so "open source" don't mean a whole lot, not today anyway. The available libraries are very immature. It's clearly a nice promotion for SkyWater, one I am enthusiastic about, but nonetheless not the shimmering beacon you're looking for.

You already know this: time is your most precious commodity. Don't bumble your way through a thinly disguised and immature FOSS offering. Cadence Virtuoso online training is just $3k per seat per year[1]. That said, I'm completely talking out of my rear. I've no idea if the training is actually useful without having a license for Virtuoso, where the webs say license costs are 6 figures per seat. I'd enroll in a university program to get access ... [2]

I just suggest this based on your stated goals, to be able to have enough proficiency to use professionally. Certainly you don't need 10,000 hours, and some of that is amortized by related experience, but time is your #1 enemy here, not money. Any money you can spend to jumpstart things is money well spent. OTOH if you just want to enjoy exploring IC design in a noncommittal hobbyist way, as a learning "experience" ala MasterClass, then this project does seem an excellent starting point.

SkyWater is a "trusted foundry", whatever that means, apparently completely US-based. Therefore, I think the most valuable thing that could ultimately (say 5 years hence) come out of this would be for OpenTitan to be "ported" to ASIC and to the SkyWater process. 130nm is large but for this application, for IoT in general, for anything not a mobile handset, it would be powerful. Imagine a Raptor TALOS workstation with an OpenTitan RoT! Or, your own design PCIe card with your own fabbed and X-Ray verifiable RoT. Powerful.

[1] https://www.cadence.com/content/dam/cadence-www/global/en_US... (slides 3 and 4)

[2] https://www.cadence.com/en_US/home/company/cadence-academic-...

Heck, it's a whole 10 sq mm. I'm sure they could work something out to combine multiple smaller projects into one slot, muxed by the supervisor.

and then you're going to do a secondary saw operation? $$$

IC design does not need a masters or PhD, that's just what companies want to hire. The old school guys do not have these accreditations and somehow they're still doing fine.

-Engineering PhD

It's not "IC design" that's orders of magnitude more complex. It's "IC implementation" where the complexity lies.

Design for test, Logical verifcation (simulation, logical equivalence checks, electrical design rules), Physical implementation (library development and characterization, floorplanning, place and route, signal integrity), signoff (timing closure, electrical desing rules (again), physical verification, OPC) all require highly complex tools to automate. For large designs you will have people dedicated to each individual step because the ways in which things can go wrong -- and the absolute necessity of things going right to get a working chip -- are legion. And there's no substitute for experience to know the right questions to ask.

It's like the difference between driving your car across the country and flying to orbit. If you make a wrong turn in your car you can just make another turn or backtrack (edit the source code and rebuild). If don't have the right torque on the tank strut bolts on your rocket, "You will not go to space today".

Source: 30 years in the ASIC and EDA industries doing chip implementation and EDA tool flow development.

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