Die shrink: How Intel scaled down the 8086 processor | Hacker News Reader

Die shrink: How Intel scaled down the 8086 processor

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119 pointsmnem23 comments

Die shrink of a processor I worked on in the 90's, the C-Cube CL4010.

Looks like the design changed even though it was functionally equivalent.

http://www.w6rz.net/IMG_0044.JPG

Maybe to help manufacturing yield improvements? Sometimes a design change can improve part yield, and if you're already having to validate it for a die shrink anyway, it might be worth the cost of a redesign. Especially if the chip is composed of IP Blocks (or a similar analogue.)

That's really neat! Was there ever public documentation on the microarchitecture of these chips? I seem to remember them from back in their day and it'd be neat to see how they worked.

Unfortunately, this was around 1993-1995 and PDF's weren't in widespread use yet. Everything was on hard copy and I'm sure I tossed that years ago.

It was a fully custom 32-bit ISA and we had a custom back-end for GCC (although a lot of the code was written in assembly language). The I-cache was manually loaded. The C compiler had a mechanism to detect when the instruction pointer went off the ends of the current I-cache page and automatically loaded the target page. I can't remember if it was some sort of trap or if it was hard-wired in the code.

The chip had some specialized processing units, most notably a motion estimation engine that did billions of MSE operations per second and a DSP engine for the DCT/IDCT.

The chip was used for the DirecTV roll-out in 1995. I remember watching the OJ Simpson chase on a test receiver in the lab at C-Cube.

The original DirecTV encoders used the CL4000 and were actually MPEG-1 at 720x480 resolution. They used 8 chips to parallel process the image in strips. When the CL4010 was ready, the encoders were upgraded to MPEG-2 with a 12 chip architecture (4 chips added to do the additional field/frame motion estimation).

Neat! Thanks so much for the run down!

Are you sure the design changed and it's not just the way light is playing off the surface at the different sizes?

Does anyone have experience with die shrink on modern chips? How does it compare?

There's a lot of options with different tradeoffs. I've seen both where they keep most of the mask intact like your 8086 example, and where they just didn't make RTL changes, but still go through the whole tape out process again (normally with what were pretty hands off standard cell designs in the first place).

The Zen+ shrink was neat because they only shrunk the individual transistors, but kept their position and spacing the same. So the die was the same size, but just more gaps between gates. I've got a theory the folk who normally sit between RTL and layout were running around with their hair on fire from the Spectre revelations, and didn't have the bandwidth to help with low hanging micro optimizations you'd normally see with a shrink, but only have rumors and speculation to back that up.

What's the point of doing a shrink, but keeping the die size the same? Power efficiency, using a new fab?

The choice between better power efficiency, better clock rates, or some combination of the two.

Additionally, in the Zen+ case, it was a shrink from TSMC 14nm to TSMC 12nm, which you'd be excused for thinking about as TSMC 14nm+++++. Not a lot of design rules changed.

The shrink is usually done at the fab. I.e. layout designers pretend to draw in a higher nm node, then the fab scales the layout. Like 28->22 nm, or 16->12 nm and so on.

Transistor models stay roughly the same, often they include SPICE command .option geoshrink=x where x is a desired shrink factor.

There may be additional DRC rules for the layout in the lower node that necessitate corrections.

Took me a bit to figure out why Intel was researching mortal psychotherapists, lol.

I looked into the differences between the 8086 and 8088 because the 8086 was selected for most designs when the 8088 was already available.

Turns out the 8088 has less compute power. I think all Intel chips since than have higher numbers if they are more powerful, not if they are more recent.

8088 is simply a 8-bit version of the 8086, thus the "8" in 8088. It was developed because the 16-bit 8086 was somewhat ahead of its time - back then, everything in existence - PCBs, interface and driver chips, backplanes, connectors, etc - was still centered around the 8-bit data bus and it was impractical to redesign them. Until they start becoming obsolete, allowing 16-bit successors to take over gradually.

I'm not sure what you're saying. The 8086 was introduced in 1978, while the 8088 was introduced in 1979. The 8088 is essentially the same as the 8086, except the external bus is 8 bits instead of 16 bits, which reduced system costs. The original IBM PC selected the 8088, not the 8086.

The Intel chip numbers are all over the place. For instance, the 8048 series had parts ranging from the 8020 to the 8749; the "7" indicated EPROM.

Contrary to what the others are saying, 8086 and 8088 have more differences than just bus size. Certain instruction have different timings, and as I vaguely remember, pipeline depth was also different.

The effect of the 8-bit bus and prefetch queue are described in detail here:

http://www.jagregory.com/abrash-black-book/#the-8-bit-bus-cy...

The 8086 and 8088 CPUs differ essentially from one another by their respective data bus widths (the 8086 uses a 16-bit data bus, and the 8088 uses an 8-bit data bus). The Execution Unit for each processor is identical. The Bus Interface Unit for the 8086 incorporates a 16-bit data bus and a 6-byte instruction queue whereas the 8088 incorporates an 8-bit data bus and a 4-byte instruction queue.

See the iAPX 86,88 User's Manual http://www.bitsavers.org/components/intel/_dataBooks/1981_iA...

You contradict yourself, when you say "differ essentially from one another by their respective data bus widths" and "8086 incorporates a 16-bit data bus and a 6-byte instruction queue whereas the 8088 incorporates an 8-bit data bus and a 4-byte instruction queue.". In a sense 8088 has shorter pipeline. Shorter pipeline makes optimization techniques for 86 and 88 different, irrespective of the bus width - I mean, even if you slap 16 bit bus to 88, without changing the queue size, most efficient optimizations would still be different between these 2 CPUs.

I'm literally quoting from page 4-1 of the Intel 8086/8088 manual.

And how the fact that you are quoting from some manual contradicts the fact that speed is different because of different pipeline depth?

How long was the 8086 in production for?

The 8086 was in production from 1978 to 1998.

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