Intel to use nanowire/nanoribbon transistors in volume ‘in five years’ | Hacker News Reader

Intel to use nanowire/nanoribbon transistors in volume ‘in five years’

anandtech.com

52 pointsrbanffy25 comments

I think it can be difficult to appreciate the problem that 'gate all around' transistors solves. For all their "layers" semiconductor devices have been essentially stuck in 2 dimensions[1] since the beginning of time.

This is the key point (from the article) : One of the key benefits of these GAA transistors is that the transistor can be specifically tailored to the operational requirements.

Basically, in the "way back" times there was exactly one type of transistor characterized for the whole process, so you got to use the "P" version or the "N" version but always the same transistor. This got upgraded a bit when companies figured out how to mix more than two (I've seen up to seven) types of transistors in the mix so that you could have "drive" transistors for I/O, and "internal" transistors (for logic) and "buffer" transistors that would move clock signals further on the chip or with a sharper turn on or turn off characteristic.

If you can create a process where the GAA transistor is parameterized in the process (by which I mean the circuit designer can say "I want this parameter to be X, this other to by Y, and this third parameter to be Z all at frequency Q" for each and every transistor in the part, that is huge. I would guess that conservatively that adds 30% to your scaling efficiency.

Mask tweaks would be harder but at these scales I don't know that anyone is going in and "fixing up" problems with an e-beam on die these days.

Anyway, the result is going to be some pretty amazing parts when this stuff is integrated into the pipeline, especially mixed signal parts (some analog / some digital) because that is an area that can really benefit from a bunch of different transistor sizes.

[1] EDIT: Referring here to device geometry in the X and Y dimensions. While these determine some parameters, typically such transistors were all of a very similar size (back when the process node name like "1 micron" was equated to the transistor feature size, unlike today where its more of a measurement of something such that the fabs can brag about how small it is)

When you said “2 dimensions” I assumed you were referring to the spacial dimensions X,Y.

Reading the rest of your comment, it appears you were referring to transistor parameters?

Edit: corrected tapographical error to spacial.

Excellent observation! Yes I was referring to geometric dimensions when I said "2 dimensions" but from a device physics perspective changing those two dimensions also changes the device parameters :-) (in classic CMOS/NMOS processes I have seen it characterized as leakage and voltage threshold)

You are correct though it was worded in a confusing way.

Ah, I see. I initially thought you were going to launch in to three dimensional chips.

Thanks for clearing that up, makes sense now.

In other news, Ampere [1] expect to launch their 128 Core ARM Chip by the end of this year.

I know nothing has really happened yet but I am already feeling a little sorry for Intel.

[1] https://www.anandtech.com/show/15871/amperes-product-list-80...

couple of items which struck nicely

>Q32-17* - 32 cores and 4TiB RAM is 58W TDP, i.e. basically beefy laptop level

>4-Wide superscalar aggressive out-of-order execution

So, with the last item being the key to modern CPU performance, it isn't just Intel, it is probably whole x86 family will feel the pinch. Add to that Apple's move to ARM. Sounds like a promise of great times to come - i.e. competing architectures.

Maybe they should worry about 10nm first :)

That's not how the industry works.

They have always multiple technologies in different stages of development.

Intel failed one major technology node and it will hit their profits hard,but anyone who thinks that it has any effect to their 7nm node don't know how this works.

Just some lighthearted fun poking at Intel :) They were market leader long enough they can beat a few jokes I think.

I do wonder though whether the fact Intel failed on 10nm means they're likely to fail on 7nm and below as a result of a failed culture? Certainly the technology looks very different for the next node (or so I assume) and maybe Intel just made a bad assumption/went down the wrong path that cost them many years for 10nm, but the fact they weren't able to insulate against the risk does seem somewhat worrying, right?

> maybe Intel just made a bad assumption/went down the wrong path that cost them many years for 10nm

That's exactly what happened. They scaled it at over 2x density (I'm not expert, but apparently it was usual to aim between 30 and 40% increase), being confident that they had such a lead they could go for such an ambitious goal. That failed miserably. That is the "botched" 10nm node that never came to be. The current "10nm+"or "10nm++" process is a sensible fix over that, which should put them on par with TSMCs 7nm (actually slightly ahead, but it´s within 5%, see [0]). But having botched it in the first place made Intel take far longer, and TSMCs not only caught up, but surpassed them.

And yes, Intels 7nm node is independent from that (though they say they've learned the lesson from 10nm and have taken safeguard measures should problems with a new node arise again). There's very little information around it, so can't tell much. But if it's on track, it should arrive close to TSMCs 5nm and be a contender to it.

[0] https://en.wikipedia.org/wiki/7_nm_process#7_nm_process_node...

Everybody must make some big chooses and commit to development path. Risks are huge. Intel chose not to use EUV and it was the wrong one.

People forget that 2 out of 4 companies failed in this round. It was not just Intel. GF completely quit the race of high-end microprocessor nodes in the middle of development.

I'm totally unaware of the Intel-failed-at-10nm story -- is there somewhere good to read an intro to that?

This talks about it some: https://www.extremetech.com/computing/295159-intel-acknowled.... I hadn't read it but this article seems to talk about it as well: https://www.nytimes.com/2020/03/01/technology/intel-culture-....

Alternate title:

Intel to use 10nm process 'five years ago'

I wonder if advancements in semiconductor manufacturering will eventually help bootstrap molecular nanotechnology.

Excited to see this in ten years.

You think this is a knee jerk reaction to Apple's ARM line announcement and Japan's TOP500 ARM headlines?

Doubt it, to quote Jim Keller "We’re all building nanowires in the fab. Intel, TSMC, Samsung, everybody’s working on it."

It seems like there was plenty to still work on then. What's up with Jim Keller's abrupt resignation? https://www.anandtech.com/show/15846/jim-keller-resigns-from...

I was wondering about his resignation as well. He does have a history of showing up, pushing the technology bounds, optimizing the fab and design processes, then moving on to do it again. Maybe he just hit his benchmarks for work completed and wanted a new challenge.

He left due to a close family illness.

Do you have the interview where he says that? I had never heard about it until today.

Also TSMC trouncing it across the board.

> ... 'In Five Years'

So what does Intel want us to do today, make a circle around a bonfire and sing praises?

Seems like too little, way too late. In five years we're going to see an entirely different landscape in regards to the popularity of arm processors.

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