Hacker News Reader

Very interesting. It may seem that the bad performance of the ADC instruction is due to bad design of the ALU, but I think this is more of an example of how replacing (single sequential task) by (several parallel tasks whose results are combined at the end) allows the CPU to finish faster.

View on HN

He’s testing on Haswell, where (at least according to Agner Fog) ADC has an extra uop compared to ADD. On Broadwell and later, non-memory ADC is a single uop with a single cycle of latency. He would probably see a big speedup on a newer CPU.

It's a data flow problem. Four ADD instructions can be parallelized. Four ADC instructions have to run serially.

And in particular, sixteen ADC instructions in four chains shouldn't run any slower than sixteen ADD instructions (assuming four execution ports and a large enough reorder buffer), but a: Haswell sucks, and b: even on properly-designed CPUs, making parallelization easier is almost always some kind of win, because general-purpose CPUs always have dispatch overhead.

Reply on news.ycombinator.com