Comment by ra1n85 | Hacker News Reader

Comment by ra1n85 | Hacker News Reader

For many years, the most popular routing platforms (i.e., boxes built by Cisco) performed IP packet forwarding and management functions on the same processor (often a RISC architecture). In cases where packet rate was high, it was possible for devices to become unresponsive or lose critical protocols responsible for sharing routing information.

In the last 15 years there has been a hard move away from these architectures. Almost no packets are forwarded by the same processors running management and control plane functions anymore. This is mainly because the required traffic rates today need dedicated silicon purpose built for the task (the Broadcom Tomahawk3 can do 12.8 Terabits/sec above a relatively small packet size).

I don't know how things will shake out for the Linux world and x86 packet forwarding given the trend and lack of real performance in the kernel. Right now, your best bet when it comes to Linux and high network throughput/packet processing requirements is to just bypass the kernel entirely with DPDK, a "smart" NIC, or XDP.

> I don't know how things will shake out for the Linux world and x86 packet forwarding given the trend and lack of real performance in the kernel.

That's pretty much settled isn't it? It was settled in the same way the "it got too much for the general purpose CPU" problem always gets settled - you do it in custom silicon, and define a standardised interface.

That's pretty much what happened with 3D graphics where the standardised interface was OpenGL (but now seems to be up in the air). It's also pretty much what's happened in AI with standardised libraries interfacing to custom hardware, and it's what happened with networking.

For networking, the interface standard is OpenFlow. So, if you think it's possible you will need to handle links of about 1Gbs or over in the future, you do your networking using an OpenFlow implementation like Faucet. If it's not much above 100Mb/s the Linux kernel module that implements OpenFlow, called openvswitch, will be fine. Otherwise use some custom hardware.

Openvswitch has been around since 2009 - so it's not exactly a new thing.

I was intrigued by your comment about the Tomahawk3. Turns out there is a Tomahawk4 implemented in 7nm which has twice the performance. Thank you for tipping me off to these devices:

https://www.broadcom.com/company/news/product-releases/52756

Yep, though it’s not commercially available quite yet. Likely only shipping samples to switch manufacturers at this time.

These is the most up-to-date article I've seen on these matters https://lwn.net/Articles/787754/ https://lwn.net/Articles/629155/

I wonder if there's an economic argument, at useful scales, to using FPGA's in general purpose servers to accelerate network performance. The purpose-built ASICs would win on cost-per-unit every time, but the FPGA would have some adaptability to new protocols or algorithms that the ASIC wouldn't.

Yes, Azure uses FPGAs for networking. Programmable NPUs like Netronome or Pensando are a middle ground that are more cost-efficient than FPGAs for most needs.

Ive been waiting for mainstream workstation motherboards with this capability for years. Presumably a pci card is how this would be handled in practice for now. My naive take is that toolchains are still too convoluted and bogged down with licensing schemes to deliver the kind of real-time highly integrated adaptability this would require for individual users. Would be great if the barrier to entry has in fact dropped enough that university-sized networks could consider them.

There's some cool tech going on at barefoot (https://barefootnetworks.com/)

I don't know much about the technical details, but the pitch I've heard is that it gives you ASIC level performance with more flexibility to reprogram the chip (not full FPGA).

Yeah, it's an interesting approach. They're basically allowing you to define packet processing with P4 on their Tofino family of chipsets: https://p4.org/

That said, there's only so much you can do in a chip before considerable tradeoffs are going to be made. They're not going to offer the same level of flexibility you get out of a general purpose CPU, but may not have same the restrictions of most fixed pipeline chips - their product sits somewhere in the middle. Also, P4 seems to sit in a space complex enough to make it unreasonable for most network shops - it's not for your average enterprise or service provider network.

>"In the last 15 years there has been a hard move away from these architectures."

It's been longer than that for router vendors. The move to hardware based forwarding was in the 90s.

That's not entirely accurate - Cisco open sourced VPP which they use in many products:

https://blogs.cisco.com/sp/a-bigger-helping-of-internet-plea...

https://docs.fd.io/vpp/16.09/

While they still obviously make custom ASICs, they've moved towards more software where possible.

Sorry, what's not accurate here?

Pretty much everything above their small medium business ISR routers use ASIC/NPU for all traffic possible. Which routers are you referring to?

Are those kernel bypasses better than the Linux-based RDMA we've had for ages (on appropriate fabrics)?

One problem with RDMA is that it's not compatible with existing protocols.

It's existed for a fair while as Infiniband doing Linux by-pass; the comment didn't say TCP/IP. (The general technique pre-dates Linux, of course.)

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