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This feels a bit like they just took an existing Intel design and tried to adapt it for AMD. Nothing wrong with that per se - by all accounts it's a good solid board - but it leads to weird choices like not using 56 of 64 PCIe lanes on the second CPU.

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> (...) but it leads to weird choices like not using 56 of 64 PCIe lanes on the second CPU.

The article mentions that out of a total of 128 PCI lanes, 64 are used for CPU-to-CPU communication and only 8 are used for an external PCIe device.

To be fair, a user that feels the need to cram two EPYC processors on the same motherboard is someone who is willing to pay a premium for CPU-bound computations.

There are some other potential reasons: - Simpler PCB routing (= fewer layers = cheaper board) only using lanes from the CPU closer to the slots - Slots still work when 2nd CPU is not installed without extra chips - Board is already not designed around heavy I/O use cases given lack of PCIe 4.0 support

This definitely feels like a board that's mostly intended for compute-intensive workloads that do not need much PCIe bandwidth.

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