An History of Nvidia Stream Multiprocessor
fabiensanglard.net
fabiensanglard.net
The most interesting thing to me in the progression of NVIDIA’s compute offerings is that until Volta, the “SIMT” claims were just a programming model and the hardware was actually just like any other SIMD hardware (though with automatic mask stacks). In Volta, they finally added “we can run different ops at different program counters”.
For the casual reader, the hot chips 2017 presentation is probably the easiest skim:
https://www.hotchips.org/wp-content/uploads/hc_archives/hc29...
Intel calls their process 10nm and it's weird to mention it since it was a total disaster.
So true.
It seems converting the whole SVG from "Object to Path" fixed the issue everywhere.
If I remove the "writing-mode:tb-rl" firefox renders it properly. It seems FF does not support that attribute.
I have kept both versions of the SVG and intended to fill a bug report.
http://fabiensanglard.net/cuda/g71.svg http://fabiensanglard.net/cuda/g71_org.svg
I have this weird guts feeling it will be closed as "we know. we don't support it yet. Come back later". So I abandoned the idea.
https://developer.mozilla.org/en-US/docs/Web/SVG/Attribute/P...
But the detailed documentation it links to does not:
https://developer.mozilla.org/en-US/docs/Web/SVG/Attribute/w...
I had a look in Bugzilla and couldn't find anything specific to tb-rl, but did find an ancient meta bug for writing-mode which links to millions of other bugs:
Are tensor cores idle during 3D gaming? How do they differ from the regular Shader Units? Why are they more efficient?
They are basically a big array of ALUs hard-wired in a grid to do a matrix multiply: The connectivity between ALUs is baked into silicon: no general purpose register file to hold the intermediate results, just wires directly from the output of one ALU into the input of the next (well, and registers for pipelining).
No overhead for register files, instruction decoding, instruction scheduling, load/store units, cache, etc. (load/store is handled by the usual SM instruction set).
This is basically the same concept you find in any "AI acceleration" hardware (Google's TPUs, various neural-thingys you find in Phones, etc).
As for using in games, this hardware is generally idle, except for a few cases (typically because Nvidia did the work to light them up):
- upscaling from lower resolution rendered products to higher resolution (Nvidia markets this under the name "Deep Learning Super Sampling"), which is basically taking a derivation Temporal Anti-aliasing and mapping it onto the tensor cores to exploit that hardware
- Doing CNN-like denoising and reconstruction of a noisy ray traced image.
Nv is making a use for them via https://en.wikipedia.org/wiki/Deep_Learning_Super_Sampling
> How do they differ from the regular Shader Units? Why are they more efficient?
They basically implement a special-purpose, single-instruction 4x4 matrix multiply operation with 16-bit floats. https://www.anandtech.com/show/12673/titan-v-deep-learning-d...
The tensor cores are used for real-time raytracing, ML-based anti-aliasing during gaming, and other features. The Turing whitepaper has a lot of information on that.
https://www.nvidia.com/content/dam/en-zz/Solutions/design-vi...
A more generic answer to this question is that everything NVIDIA puts in their GPUs is for the gaming market. Other use cases are incidental.
I expect we'll see some more compelling uses of it in the next few years, given that it took until the last year or so to see games start using it in a way that wasn't just tacked on. (It makes sense that Control was one of the first titles to use it extensively, since they were publishing talks about GPU raytracing well before the hardware was in anyone's hands)
Also, once the hardware is more ubiquitous (e.g. in consoles), some of the features provided by raytracing will make the game development process much simpler even if the results are only marginally better for some of the presented hybrid use cases.