Writing a RISC-V Emulator from Scratch | Hacker News Reader

Writing a RISC-V Emulator from Scratch

book.rvemu.app

130 pointsvcsilva15 comments

> This is the book for writing a 64-bit RISC-V emulator from scratch in Rust.

Next I want to see the book for writing a 64-bit RISC-V emulator from rust in Scratch ;)

The upper case S in the title made me believe for a second that they did it in Scratch :)

Since I got into programming with Scratch, every time I see it capitalized in a HN title I get my hopes up that someone made something really cool in it. Alas, it never happens.

This [0] project might be one of my favourite ones I've seen in Scratch. I don't know how they managed to correctly keep everything together, considering the size of some of the internals.

But it does do almost everything I would expect.

[0] https://scratch.mit.edu/projects/159487877/

This looks like a nice project, and I will check on its progress. So far only two of the advertised steps are there.

Reminds me, I started a RISC emulator project on a holiday - and then forgot about it when the holiday was over :o

Not sure if combining "learn rust" and "learn RISC V" at the same time is a good combination for a large audience, it will depend on the reader.

Maybe the intended audience is someone who knows enough basics and has plenty of motivation for/prior knowledge of/interest in both topics. And then, for good content, there will always be an audience.

> Not sure if combining "learn rust" and "learn RISC V" at the same time is a good combination for a large audience, it will depend on the reader.

Heh, this is _exactly_ the combination that appeals to me, or at least would have before I learned either of them.

It looks like it's the season for hobby RISC-V emulators, because I've also been working on one.

https://github.com/michaelmelanson/riscy

The tricky part here comes when you have to run non-trivial programs. Mine currently passes the basic test suites, but it still fails in the C runtime startup when executing programs compiled with GCC. My next step is to do co-simulation with another emulator in order to find out where their execution states diverge.

> Mine currently passes the basic test suites

The tests in riscv-tests are not complete enough to indicate strong compliance. I have found several bugs in my implementation that were not caught by them.

> but it still fails in the C runtime startup when executing programs compiled with GCC

The biggest issue I have seen with running C programs is that people don't have the system calls that C runs on startup. In a log from rv8, you need brk, uname, readlinkat, and mprotect. So without those you shouldn't be able to get a program into user code unless you make a custom entry point.

Source: I am the maintainer of RARS (https://github.com/TheThirdOne/rars)

> The tests in riscv-tests are not complete enough to indicate strong compliance. I have found several bugs in my implementation that were not caught by them.

I've noticed that, yes. They got me pretty far, but there's something I'm doing wrong and I haven't been able to find what. That's why the next thing I'm going to try is co-simulation.

> The biggest issue I have seen with running C programs is that people don't have the system calls that C runs on startup. In a log from rv8, you need brk, uname, readlinkat, and mprotect. So without those you shouldn't be able to get a program into user code unless you make a custom entry point.

Yes, that hasn't been a problem so far. I've written minimal implementations of a few (so far: fstat, brk, exit) as I've gone along. https://github.com/michaelmelanson/riscy/blob/master/emulato...

Thanks for your interest! I'm an author of this book. This book is very beginning as you mentioned and I'm still working on it.

I already succeeded to run xv6 in my RISC-V emulator and wrote a blog post "Made a RISC-V Emulator Running Xv6": https://d0iasm.github.io/blog/risc-v/2020/04/03/xv6-on-my-ri...

I have 2 different RISC-V emulators and its goals are different:

rvemu (https://github.com/d0iasm/rvemu): Can run xv6. It's trying to support Linux and make it faster in the future.

rvemu-for-book (https://github.com/d0iasm/rvemu-for-book): Reference implementation for the book. Simpler than original one.

What does opcode 0x41 does? It's stopping the emulator when I try to run it on fib.text. Otherwise it's a pretty decent tutorial. I've also been following Stephen Marz's tutorial on bringing up a basic operating system on RiscV 64, going to use the two together.

Could you please elaborate on what the differences between the two implementations are?

The main difference between them is the number of instructions are supported. Rvemu supports RV64GC, while rvemu-for-book will support RV64I and instructions that xv6 uses (e.g. mul).

Also rvemu will support a device tree but rvemu-for-book won't.

Unfortunately it seems like the privileged instruction set is not yet covered. Also, I think that the arithmetic needs to have explicit wrapping? Otherwise it’ll overflow and cause a trap in debug builds I believe.

Making an OS for RISC-V in Rust: http://osblog.stephenmarz.com/

This will be interesting once it is finished.

As it is now, it is just a skeleton, and thus not worth the light of day.

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