How the Father of FinFETs Helped Save Moore’s Law
spectrum.ieee.org
spectrum.ieee.org
It's also impressive he made impacts in so many different aspects, transistors, solar cells, optical, etc. Well deserved award.
> His career soon took a detour because semiconductors, he recalls, just seemed too easy. He switched to researching optical circuits, did his Ph.D. thesis on integrated optics...
I was very disappointed to go the article and find that Hu does not in fact surf:
> Hu had heard about the DARPA funding from a fellow Berkeley faculty member, Jeffrey Bokor, who, in turn, had heard about it while windsurfing with a DARPA program director
[0] http://www.eng.auburn.edu/~agrawvd/COURSE/READING/LOWP/Boh07...
[1] https://cartesianproduct.wordpress.com/2013/04/15/the-end-of...
>"The main problem was power. As features grew smaller, current that leaked through when a transistor was in its “off” state became a bigger issue. This leakage is so great that it increased—or even dominated—a chip’s power consumption."
How exactly does residual current start to dominate? Does this mean that current starts to leak into neighboring transistors and inadvertently turn them on?
>"Hu saw the fundamental problem as quite clear—making the channel very thin to prevent electrons from sneaking past the gate?"
I would have thought that making the channels thinner make current flow through them easier. Why does making them thinner prevent current leakage exactly?
Power consumption in a digital chip traditionally happens many ways: dynamic power is the energy consumed moving charge around to actually flip a signal at a transistor. For the same clock speed, it goes down as feature size goes down, because gate capacitance is smaller so less charge needs to be deposited/removed on the gate to raise/lower its voltage by a given amount (also increases with clock speed for the same feature size, because more charges/discharges per unit time). Static power is current draining through (often, always?, parasitic) resistive paths, and needs to be either be provided all the time, or requires a minimum clock frequency so that the voltage is still detectable when you need to. This actually drives the minimum refresh rate on DRAM.
The big change, what I understood as a surprise when it happened (I was an undergrad EE while this hit the industry), was when insulator structures got thin enough that electrons were actually quantum tunneling "through" them. Now you've got a new parasitic path for charge to drain away, and on top of that it changes the performance of your transistor. At the time, and I want to say this was the 45nm process node, but it could've been 90nm, gates oxides (insulators) were ~5 atoms thick.
Unfortunately, I didn't really stick with this part of EE, so I'm not sure what to say about the thinner channels.
I guess sum total of leakage current in all the OFF transistor coming up more than the sum total of all the ON transistor current. Assuming at any point of time, more than 50% transistors are OFF, there are so many OP codes in x86/64, only few of them could be active at a time.
See this Wiki article. What is commonly called "leakage" is more formally called "subthreshold conduction". The two n+ areas of the FET are the source and drain. In that particular picture a conducting channel between those two would be formed when Vg is positive. The problem is that, for a variety of reasons, when the devices are that small it is difficult to keep current from flowing between drain and source even if Vg is zero. https://en.wikipedia.org/wiki/Subthreshold_conduction
In a "traditional" FET, as shown above, the channel is formed in the region below the gate.
If you look at the "FinFET’s Features" illustration in the IEEE article the orange area is where the channel can be formed. It is no longer simply "below" the gate, but instead exists as a three dimensional structure. This gives the gate voltage more control of the current flowing between source and drain.
You can reasonably ask: why not make it really small and make sure it closes. The reason is that you need current to drive the computation process.
So anyway, you balance these factors at each node, which is what BSIM lets you do.
Interesting so is this why we see the research into carbon nano-tubes or is that something else?
>"So anyway, you balance these factors at each node, which is what BSIM lets you do."
What is BSIM here?
The below might be inaccurate. It's been a while since I last took semiconductors.
Decreasing length increases speed because there's less parasitic capacitance between the gate and the current channel underneath it, so less charge needs to be pumped onto the gate to turn the mosfet on.
An npn mosfet turns on by putting a positive charge on the gate that pushes away positive holes and pulls negative electrons into the channel under the gate. This turns the channel region from a depleted region that behaves like undoped silicon which is an insulator to a region filled with negative charges like n-doped silicon that can conduct current. But to do this, you need to put charge onto the gate, The larger the area under the gate the more charge you need to put on it and the longer it takes, or in other words the parasitic capacitance increases. This parasitic capacitance is proportional to W x L, but since decreasing W (the cross-section of current flow) decreases the current going through the MOSFET when it's turned on the approach before FinFETs was to use more precise etching technologies to decrease L.
The problem with decreasing L though is when the MOSFET is off, the small distance of "undoped silicon" under the gate isn't enough to stop current from leaking past it. You could decrease this leakage by decreasing W, but then when the MOSFET is on the max current is lower and that slows down other components down the line. This on current has to go on to charge up other gates and turn on other components.
What a FinFET does is ask, instead of turning on a MOSFET channel by having the gate act on it from just one side, why not have the gate act on it from 3 sides by sticking it out of the silicon substrate and surrounding it by the gate. Now, we can have small L and small W to decrease leakage, as well as a larger on current that's equivalent to what a regular mosfet with a larger W would have.
I'm not actually sure what this would do to the parasitic capacitance I mentioned earlier, since this should increase the "width" of the channel that the gate is contacting. Maybe the 3D configuration actually ends up reducing this capacitance? 3D EM fields is a whole other beast compared to 2D, and we're also talking about nanometer scales and semiconductor materials here. But it definitely allows you to pack transistors closer together.
>"What a FinFET does is ask, instead of turning on a MOSFET channel by having the gate act on it from just one side, why not have the gate act on it from 3 sides by sticking it out of the silicon substrate and surrounding it by the gate"
This was a nice way of articulating this and makes good sense. Thanks.
Could you elaborate on this? Do you mean bringing the the process node/fab online? More so of a beast than other other nodes? Cheers.
Yes, I meant bringing up the process node.
Yes, more so than other nodes, but for context I only go back to p854, so earlier might have been worse.
The people in charge of the model need to be very smart, very diplomatic, and very thick-skinned because every release they have literally hundreds of managers and project leads screaming at them.