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Comment by kabdib | Hacker News Reader

I was told by Leonard Tramiel (who was my manager at Atari for a while) that the world record for a production 6502 was 25Mhz. This was demonstrated one Friday evening, some time after the beer fridge had been opened in one of the labs.

I don't know if they applied any kind of external cooling, or what the benchmark was. Probably it was "keep cranking up the clock until pins stop wiggling or smoke comes out." Not very scientific, but quite entertaining.

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One of my old companies (InformASic) developed a VPN solution for serial communication. The product LinkShield (later renamed and spun off to form CrypTango) was implemented as a small ASIC. The main CPU was a 6502 clone with memory protection. We clocked it at 33 MHz, but usually ran them at 25 MHz in the products. That 6502 clone was cycle correc, that is the number of cycles required for an instruction was the same as for the original MOS 6502.

Nowdays you can quite easily to a 6502 implementation in a FPGA running at 100 MHz. Esp if you allow the design to use more cycles for some instructions.

Sadly the product never took off and the companies folded. I have some chips somewhere. Googling at least revealed a picture of the product:

https://www.google.com/imgres?imgurl=https%3A%2F%2Ffarm3.sta...

From the Commodore book, about the early 80s:

"We actually made a couple of really hot processors for a chess tournament for somebody. He literally water-cooled it, and he ran it at something like eight megahertz. It was just ridiculous how fast he ran it."

Earlier it was explained that some processors coming off the production line could run faster than others, and they could test for it to pick the best ones for such purposes. They didn't end up increasing the clock speed for released computers, as other components could not keep up.

There's an FPGA 65C02 core running at ~73Mhz. https://github.com/MorrisMA/MAM65C02-Processor-Core

18 MHz, actually -- the FPGA clock speed is 73 MHz, but it executes the equivalent of one 6502 clock cycle in four of its clocks.

That being said, this was implemented on a budget-line FPGA from 2006 (XC3S50A - a small Xilinx Spartan-3A). A modern performance-line FPGA would probably hit a couple hundred MHz easily.

It's still surprising how little relatively to the level of perceived performance have IPC count improved since seventies.

The perceived performance for an average desktop has been pretty stagnant since, I don't know, at least the mid-nineties.

Softare expands to fill the CPU available.

AKA Wirth’s Law[1]: “Software is getting slower more rapidly than hardware is becoming faster.”

[1]: https://en.m.wikipedia.org/wiki/Wirth%27s_law

Software is being produced faster though.

Didn't cars also follow that pattern?

There was a huge perceived improvement when SSDs first appeared.

It seems to me that computational throughput has improved exponentially, but latency for input tasks etc. has in fact worsened in many cases.

Per TFA IPC has improved by about factor of 5, assuming a 3GHz machine runs BBC micro at equivalent performance of 15GHz

Reality for (SIMD) integer math is probably closer to 1000, floating point... probably 100000.

You're wrong :)

IPCs for 6502 or Z80 (4x "faster" clock but 3-6 cycles per machine cycle) processors were at the count of clock cycles per instruction

Even a measly 386/486 were much faster than that.

Enter the Pentium with the ability to execute 2 instructions in parallel.

IPC count were the big gainers recently as well

It is still only 20-30 fold at max on average. So much more came from many thousand fold clock speed increase, and much wider execution paths.

A new stock 65c02 from WDC can do 20mhz. So this FPGA version @ 18mhz doesn't sound any better. Though I'm sure on a modern FPGA one can do more than that.

Can anyone with an electronics background explain why it's so hard to clock a 6502 higher than a handful of MHz, when modern chips can do 1000x that? Is it just larger transistor scale leading to excess capacitance / slower switching?

One reason is that: transistor size and switching speed. Though the technology of the 6502 probably could go 50MHz? 100MHz? Not sure. Would it be equivalent to 74HC TTL line? Again not sure

But the main (basic) reason is that the internal logic blocks don't worry too much about processing and arrival times beyond the speed at which they need to operate. What's simultaneous at 1MHz might be not so simultaneous at 10MHz or 100MHz

Another (advanced) reason why overclocking it might be hard is EM interference inside and outside the chip.

The 6502 has very limited pipelining, and every CPU cycle is tied to a memory access with no support for wait states or stalls. At 1 MHz it can work with really slow memory (roughly 500 ns), but at 10 MHz it needs ~60 ns, and at 20 MHz something like ~20ns. The architecture simply wasn't designed for anything above single digit clock speeds.

"until pins stop wiggling"?

Maybe the pins got so hot they melted into the board?

I think it should be “start wiggling” as that makes more sense.

Wiggling pins is what a computer does when it is working.

Wiggling a pin - ie: toggling it. Basically means "activity on the pins"

https://www.cypress.com/blog/technical/more-pdl-examples-wig...

The pins don't physically wiggle. "pins wiggling" is a common metaphor for "the voltage level on a pin is changing".

As a signal driver is toggled at increasing frequencies ('cranking up the clock'), the signal amplitude (voltage difference between the 'high' and 'low' period) starts to drop. At a high enough frequency, the signal will be indistinguishable from noise and 'stops wiggling'.

> At a high enough frequency, the signal will be indistinguishable from noise and 'stops wiggling'.

It's not that the signal will be indistinguishable from noise, but that the CPU will stop working correctly, so its outputs will stop toggling (or will toggle in unexpected ways).

I was actually thinking about catastrophic failure, as in something on the chip burning out and making the clock stop.

My guess is that they were probably cooling it with beer (or at least cold beer bottle bottoms) to get that last critical Mhz, before drinking the beer.

I had an impression that they might be talking what a digital I/O pin looks on oscilloscope.

Scopes lock at first rising edge after last horizontal scan, so display starts at H, then drops to L after how long CPU held that pin high. That creates ￣￣l＿ lines on the screen superimposed to one another, X position “wiggling” ￣lll＿ depending on how many consecutive H bits just happened to be sent.

When the CPU halts, the pin would flatline at H or L and you’ll know.

Euphemism for when you don't see output pins transition state on a measuring instrument, e.g. oscope.

I love reading the stories about overclocking attempts (actually that scene doesn't seem to be much of a thing anymore?), people bolting pipes on top of CPU's and filling them with liquid nitrogen, nearly supercooling the CPU's and breaking speed records.

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