It's the other way around: DRAM accesses are slow, that's why we need caches.
> translation (maybe with TLB miss)
In most architectures, the caches are physically addressed, so TLB lookups occur before even L1 cache access. Successful TLB lookups are extremely fast! And you can't skip the TLB, even if you don't have any data caches.
You are totally right that if you can make the resultant communication speed faster you could theoretically do away with caches. However this approach wouldn’t solve that problem on its own. Also forget not that cache is expensive and DRAM is cheap!
Yes I’m aware that caches can be physically addressed and you could reorder the sequence I described. No you can’t skip the TLB, but a hit will be faster since you don’t have to perform translation.
So to see if a memory location is contained in a cache line, a TLB lookup is needed to first get the physical address? I wouldn't have expected this, can you expand on why this is the case?
With physical addresses, you just have to clear your TLB cache.