Comment by metaphor | Hacker News Reader

Comment by metaphor | Hacker News Reader

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In uni, I learned digital logic from Brown and Vranesic[1] who explicitly differentiate gated latches from flip-flops, the latter being defined as:

> A flip-flop is a storage element based on the gated latch principle, which can have its output state changed only on the edge of the controlling clock signal.

I also just pulled out my Fairchild Pocket Designer Guide (published circa 1985; inherited from a retired former colleague) which explicitly differentiates 74/54 series flip-flops from latches both in section and symbology. So there's at least 35+ years of industry convention without citing standard.

To cite one industry standard, from ANSI/IEEE Std 91-1984[2] § 4.2.1:

> Cm should be used to identify an input that produces action, for example, the edge-triggered clock of a bistable circuit or the level-operated data enable of a transparent latch

...or from § 5.9:

> The symbol for a bistable element (for example, a flip-flop) does not contain a general qualifying symbol. ... When a bistable element is controlled by a C input (Symbol 4.3.7-1) it is necessary to indicate whether this element is a latch, or an edge-triggered, pulse-triggered, or data-lock-out bistable.

In fact, symbol 5.9-2 labeled "D-type latch, dual / Part of SN7475" is distinct from symbol 5.9-7 labeled "Edge-triggered D-type bistable / Part of SN7474"...the former being what the blog discusses.

So no, this designer begs to differ.

[1] 3rd Edition, § 7.7 Summary of Terminology

[2] https://doi.org/10.1109/IEEESTD.1991.81068

You're correct. A flip-flop responds to an edge, a latch responds to a level.

However, let's go back more than 35+ years, to a simpler time. To the 1960s. To the dawn of the TTL era. Texas Instruments made a device called the 7473. It was a J-K Flip Flop. But it responded to a pulse, not an edge. Look at the function table in the datasheet: https://www.ti.com/lit/gpn/sn54ls73a

As a kid trying to teach myself TTL I never did understand WTF was going on. And this screwy behavior got fixed when TI did the 74LS73.

The data sheet makes clear the limitation, but either that text didn't exist back then, or I just didn't grok the significance of it. To wit: For these devices the J and K inputs must be stable while the clock is high.

So you're correct for at least the 35+ most recent years. :)

But there couldn't be rules without exceptions. :)

> However, let's go back more than 35+ years, to a simpler time. To the 1960s. To the dawn of the TTL era. Texas Instruments made a device called the 7473. It was a J-K Flip Flop. But it responded to a pulse, not an edge. Look at the function table in the datasheet: https://www.ti.com/lit/gpn/sn54ls73a

The 7473 next-state truth table in this datasheet is symbolically misleading; the specified timing constraints on p. 4 make it a lot more clear, and it's consistent with IEEE Std 91 terminology cited.

To be sure, 7473 is indeed an edge sensitive device; IEEE Std 91 references this as the pulse-triggered flip-flop--a.k.a. master-slave flip-flop--and its description on page 1 of the referenced datasheet corroborates this (my emphasis):

> J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition.

In other words, the internal output of master stage is opaque, while slave stage output Q/Qnot does not change until the falling edge, which is quite distinct from the output behavior of a latch.

> To wit: For these devices the J and K inputs must be stable while the clock is high.

Reading the datasheet further, the 73A variant apparently improved upon the original 73 design by allowing for input change after the rising edge (i.e. while clock state was high) so long as the specified t_su = 20ns min setup time before falling edge was satisfied. Also observe the 73A's 0ns min hold time after falling edge in conjunction with no min CLK low pulse duration; this clearly allows for much faster operating speeds by exploiting clocks with greater than 50% duty cycle. In contrast, the 7473 was capped at less than 15MHz = 1/(t_whmin+t_wlmin) = 1/(20ns+47ns) per specified timing constraints.

P.S. Props for teaching yourself TTL as a kid. I recall my pops (who's in his 50s now, if that's any indication of my age) once tried explaining clocks to me as a "computer literate" teen and that went waaaay over my head at the time. The magical allure of it all ultimitely led to the whole EE thing today.

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