Comment by Symmetry | Hacker News Reader

Comment by Symmetry | Hacker News Reader

The thing that really jumped out at me was making the channel partially out of germanium. Velocity saturation has been a limiting factor in our tiny modern transistors for a while, playing its own minor part in the breakdown of Dennard scaling. The article didn't say if the increase applied equally to both electron mobility and hole mobility. Germanium tends to be better for both but I my materials science background isn't good enough for me to guess what it'll be in a Silicon/Germanium lattice. Temperature dependence is also an equally interesting question since Germanium tends to deal with high temperatures a bit better.

This won't help with leakage issues or the increasing importance of wire as opposed to transistor capacitance. But it does look like a nice little win.

Speaking of wires, is TSMC still using straight copper or are they thinking of incorporating cobalt? Or did Intel's experience with that scare them off?

EDIT: And speaking of cobalt again, I really hope they aren't being too ambitious with this and that being too innovative doesn't bit them the way it did with Intel at 10nm. Though the rumor mill isn't sure if it was the cobalt wires or the Contact Over Active Gate (COAG) that was their main problem.

> The article didn't say if the increase applied equally to both electron mobility and hole mobility.

Electron mobility is not high in silicon, but it has never been a "blocker" before. In fact, the utilisation of strained silicon has gone down from 40nm in later nodes.

Silicon however has truly terrible hole mobility, and the wider industry has just started to realise that they have lost many years to fruitless pursuit of high electron mobility, when the real blocker has always been a pFET.

It was very prudent of TSMC to quietly continue pFET RnD, despite industry's fixation of HEMTs and 3-5 devices.

p.s. 5N is a COAG process from what they have just said.

The amount of Ge and thus strain has increased every node. All to make hole mobility better.

No one in industry was confused about HEMTs, and the needs of pfets were well known.

> The amount of Ge and thus strain has increased every node.

Not really from what I know. The compressive strained channel was dropped out for some FinFET designs, and I think tensile strained too in some because it was exploding litho layer count. Can you tell your source?

Compare the amount of money spent on truly moonshot material science like making 3-5 logic, and the amount of money spent on continuous improvement of pfet performance for mainstream applications.

From device cross sections and working at both IDMs and suppliers. And reading and visiting IEDM for a decade. You can keepmup with ost on semiwiki: but really, just work under the assumption that people in the field are not stupid and can do math.

Tensile strains has no litho impact, and counting layers in use was a job I had.

Who spent on 3-5? It got press coverage, but never was part of much logic research. It was a focus for power, laser, and led work.

Tsmc, Intel, applied, asm, and others spent vastly more on r&d than any government or academic work, and it isn't published.

I'll give you that. I haven't been involved with device and process development since around 2009, when I lost hope getting into process engineering.

So, were strained channels used with FinFETs on anything mainstream? I heard the news of number of foundries dropping straining at around the time of first finfets.

SiGe transistors have been mainstream in RF electronics for decades.

And telecom hardware, right? I think anything with high frequency requirements has been germanium forever.

I’ve always wondered why there wasn’t more germanium in my computer. I’m sort of wondering if that will change with chiplets. Say for instance a germanium MMU or cache.

You and the parent poster are probably thinking of heterojunction SiGe bipolar transistors.

SiGe bipolar transistors are fabricated on top of old CMOS processes and are relatively cheap from a fixed-cost perspective but not highly integrated and only cost/power-efficient for niche PHY layer applications.

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