I'm working on RISC-V based SoC on a Lattice ECP5 FPGA. The end project is a low cost combination signal generator / oscilloscope for aligning antique radios that I eventually want to sell. But the firmware will be RISC-V based and I think this will be a great example design for others to use for their own projects. I show one way to make an SoC purely in Verilog (no external system-builder tools needed).
Right now the FPGA boots the PicoRV32 SoC example code out of the configuration SPI-flash memory of Lattice's ECP5 evaluation board (I started with the firmware in block-RAM, but now it runs right out of the SPI-flash). I also have interrupts working, and have the gcc header file macros for enabling/disabling interrupts and controlling the PicoRV32 timer. I will soon have much more (SDRAM controller, cache, many other peripherals..).
https://github.com/jhallen/radioanalyzer
Also I will port it to this very nice ULX3S board as soon as I get one: