In short if it's not a good fit for your brain, change your brain!
In short if it's not a good fit for your brain, change your brain!
I am curious as to how your h/w experience makes it easier hacking on the linux kernel....
Go is sort of like saying "we're not going to deal with parallelism directly, just throw everything into fifos to talk to other places" mostly you can't afford to waste gates like that in real hardware (there are places where it makes sense - I've built a lot of display controllers).
I think the big difference is the way you end up thinking about time and timing holes in code (dealing with interrupts), after building gates for a while i think you tend to see the timing holes more easily
Not sure what you mean by your statement that hardware engineers are trained to think differently about it. I am not sure there's much overlap between HW and SW engineers in terms of parallelism modelling. Do you have a few examples?
However having said that I find myself designing silicon again, change is good for the brain I guess
Hardware people tend to think in terms of netlists and pipelining so they have to worry about parallism on every clock