5/3nm Wars Begin
semiengineering.com
semiengineering.com
>"Originally, the node name was tied to the transistor gate length dimensions."
then further down:
>"CPP, a key transistor metric, measures the distance between a source and drain contact."
I have mistakenly thought that node designations were based on distance between source and drain. Could someone say why gate length dimensions are the more significant measurement? The distance between source and drain somehow feels more intuitive to me. But maybe because this is easier to visualize?
That CPP metric is measuring how close together the contact vias for the two halves of the transistor can be. It's a much bigger number, but still probably just as good as a proxy for transistor density.
Something doesn't feel quite right.
It would be better to use logic density, but it is easier to use numbers we are used to.
> Historically, the process node name referred to a number of different features of a transistor including the gate length as well as M1 half-pitch. Most recently, due to various marketing and discrepancies among foundries, the number itself has lost the exact meaning it once held. Recent technology nodes such as 22 nm, 16 nm, 14 nm, and 10 nm refer purely to a specific generation of chips made in a particular technology. It does not correspond to any gate length or half pitch. Nevertheless, the name convention has stuck and it's what the leading foundries call their nodes.
The trick is, not everything else scaled proportionately. The gate lengths (mostly) stopped shrinking at around 34nm but other things kept shrinking, so the overall transistor density kept going up.
(And that assumes planar transistors. Things like FinFET or nanowire which make the transistor structure 3d instead of 2d further disconnect the gate length from the achievable density.)
In the wings there are a few semiconductor materials, from Si-Ge to In-P and Ga-A and Ga-N that are used in optical transceivers, cell phone base stations, power electronics, and military electronics. Silicon is a good, not great superconductor, and it dominates because we are good at making things out of Silicon.
An In-P microprocessor as complex as a 6502 should be able to clock upwards of 80 GHz and could run with a fully populated address space of static RAM on the chip and be able to react to fast events in real time like nothing else.
Such a chip would replace 16 5GHz cores for more mainstream computation, so if cost gaps narrowed, the In-P part might compete with a Si part in a complex chiplet architecture. (e.g. the In-P chip can be built at 1/16 the density of the Si chip and not have all this multiple-patterning and lasers trouble that Si is getting into)
> Such a chip would replace 16 5GHz cores for more mainstream computation,...
80 GHz 6502 would be about as fast as... 1 GHz x86 in integer operations, and even that is being generous.
Floating point would be several orders of magnitude worse than even that.
Typical X86 can do 64 8-bit SIMD operations per clock, 2x AVX2 instructions retired in a single clock cycle. At over 4 GHz.
But it'd sure be a beast in real-time applications... assuming signal integrity is a solvable problem.
I'd be skeptical about whether it beats an FPGA.
It's a relative difference though, that depends on what material you're building the circuit in. If you can build an FPGA to run at 1/10th the speed of a 6502, then with a sufficiently expensive process you get a tradeoff between a very weak 80GHz processor and a customizable 8GHz circuit.
I am angry for not having bought at least the 22i HD(high density) development kit, when it was available for 999USD for a time. But the software license was only valid for a year, so no-go.
They now offer embeddable FPGA IP cores targetting 750Mhz on TSMCs 7,12&16nm process.
And 'normal' FPGAs, the Speedster 7t, manufactured by TSMC at 7nm, also 750Mhz fmax.
All rather expensive and out of reach for the hobbyist :-(
So it would seem they beat FPGAs in some niches.
I question the 80ghz number given by the grandparent though. Looking at visual 6502 you're not going to get a order of better magnitude fanout on that design.
Better fanout than what?
The most useful thing I could find was this old article, but it certainly suggests that the room is there to expand: https://spectrum.ieee.org/semiconductors/materials/indium-ph...
GaAs would make for awesome switching systems, as it is a direct bandgap semiconductor, as opposed to Silicon, which requires phonon mediation. While this is a tremendous technological advantage, you have that minor problem of fabrication.
For GaAs, you need ~5 atmospheres of As gas at 550C. Not something anyone wants in their backyard, for good reason.
For InP, you need to worry about your supply of rare earth (In) elements, and all the surrounding tech needed to grow ingots of an appropriate orientation material for InP. You have to worry about the role of defects (which is what I simulated), how to dope, how to build structures.
Its not simply that it is technologically better, its that there is a whole massive ecosystem around Silicon, that for better or worse, pretty much guarantees that we are going to be running silicon based units for a long ... long time.
The joke, and there was one when I was in grad school, about GaAs and other non-Si materials was, they are the materials of the future. And always will be.
How do we break out? By gallium arsenide offering enough more than silicon does to be worth the effort. So far, that hasn't happened. It may never, except for small niches.
The problem with measuring physical features of a transistor is that once you change the design of the transistor multiple times [0] it no longer becomes meaningful to measure one specific dimension. As you can see the gate size barely changes but the transistor count keeps increasing drastically.
[0] https://www.hwsw.hu/kepek/hirek/2017/03/planar_finfet_gaa.jp...
People kind of misinterpret Moore's Law as this statement about the speed of computers but he wasn't talking about that in the paper [0]. He was talking about cost of manufacturing - and implicitly, the rate of innovation (which is throttled by how fast you can bring something to market).
Basically Moore's Law was an observation that implied that more complex electronics could be made cheaper as time went on.
And in today's marketplace, we shouldn't just look at node size and Moore's law as the complexity bottleneck, because it isn't. Moore himself talks about it in the paper.
As an example, Moore pointed out that at the time, "packaging costs so far exceed the cost of the semiconductor structure itself that there is no incentive to improve yields." Today this isn't true anymore - and while Zen2 did see a node shrink, the great innovation that made a more complex device cheaper was the move to chiplets, resulting in greater yields.
As well, Moore prophesied the rise of EDA tools and what would become hardware description languages.
"The total cost of making a particular system function must be minimized. To do so, we could amortize the engineering over several identical items, or evolve flexible techniques for the engineering of large functions so that no disproportionate expense need be borne by a particular array. Perhaps newly devised design automation procedures could translate from logic diagram to technological realization without any special engineering."
What I'm getting at in this ramble is that looking at node size and "Moore's Law" is only a small slice of the pie and not particularly interesting outside of material science. Looking back at what Moore actually wrote - his law is not "dead" outside of the advance of node size, but his advice on the innovation of every other aspect of design is moving at breakneck speed and it's very exciting.
[0] https://hasler.ece.gatech.edu/Published_papers/Technology_ov...
Here is a good visualization: https://www.youtube.com/watch?v=7uvUiq_jTLM
As the video concluded, we shall see...
The next process could flip for Intel or TSMC as each process has it's own problems, but for now I would put TSMC much further ahead of Intel in the Intel 10nm/TSMC 7nm battle.
This is not correct. 10nm Ice Lake laptops have been in stores for a quarter or more now. For example: https://www.costco.com/hp-14%22-laptop---10th-gen-intel-core...
As for desktops the recent rumors point to Rocket Lake in 2021 for the first desktop 10nm releases.
Intel is playing catch-up here to AMD and it’s showing.
5nm is coming later this year, most likely the A14 Chip used in iPhone.
Not sure if that fits the description of "complete"
There is only one fab doing anything interesting at all.
Sadly laptops are always behind in the manufacturing queue when it comes to knew technology.
I'm excited that Zen 2 is coming out on 7nm, but at the same time my mobile phone is already good enough in energy efficiency, and I don't expect real practical speed increase for the 5nm version.
Having said that, the very first users will be high end servers. It's no accident that IBM were the first to demonstrate 5nm wafers a few years ago[1], because they'll use them in their top of the line POWER chips. Those chips have incredible single thread performance, but also incredible prices (and apparently very low yields). If you're the sort of person who wonders who would pay money for that, then you're not the target customer :-) (Disclosure: I now work indirectly for IBM)
[1] https://www.ibm.com/blogs/think/2017/06/5-nanometer-transist...
Don't the smaller transistors also have higher leakage? I thought that below 10nm scaling down further would not give power benefits.
But we're not yet at the point where power density increases as fast as transistor density.
Little of your phone battery goes to the CPU. It's almost all screen and radios.
Also, graphics cards, server processors, and possibly now also automotive stuff.
“The design cost for a 3nm chip is $650 million, compared to $436.3 million for a 5nm device, and $222.3 million for 7nm, according to IBS. These are “mainstream design costs,” which means one year after a given technology has moved into production.”
The new nodes will only be used where the design costs can be recovered, which is mostly consumer and server farms AFAIK. Basically anything using the current best nodes will use the next gen nodes.
Right now you can get a 10nm Intel part in a laptop but not for the desktop.