Verilog isn't really very c-like. It is slightly more c-like than jts main competitor, VHDL. It is more c-like than lisp. But really, neither of those is saying much.

Ways it is not c-like:

- begin...end instead of curly braces

- parallelism with assign, always, initial

- tasks and functions and their subtle differences

- non-blocking assignment

- bit-oriented variables and operations

- 4-state logic (0, 1, X, Z)

- other constructs for modeling hardware like time delays, tri-state wires, drive strengths, etc.

Not to mention that SystemVerilog has taken over Verilog and adds OOP with classes, a complicated (sorry, powerful) assertion mini-language, constrained randomization, a streaming operator, and so on.

Heh, I suspect hardware folks would like a CPU which programmed well with Verilog or VHDL, and I know that trying to make a hardware description language accessible to software folks has been a pipe dream for at least 25 years. However, I don't think Verilog was the solution for Itanium, and the useful niche for FPGAs seems increasingly limited to low Size Weight And Power realms.

The FPGA projects I've seen (using very high end FPAGs, not commodity/cheap ones) seem like they're always bumping up against clock rates and making timing as soon as they try to do anything approaching what you can do on a CPU or GPU. Of course there are exceptions where the FPGA does really simple and parallel things, but FPAGs aren't a panacea.

Or you could prototype the algorithm in matlab then convert to HDL. https://www.mathworks.com/products/hdl-coder.html