The cited paper doesn't attribute performance variation to silicon to silicon variation. Only the blog post does.
> We show that this variation is further magnified under a hardware-enforced power constraint, potentially due to the increase in number of cores, inconsistencies in the chip manufacturing process and their combined impact on processor’s energy management functionality
and recommendations:
> • Characterizing node performance based on averaged performance distorts the true impact of manufacturing variation on processors on the node and therefore should be avoided
But the temperature of the silicon itself has a lot to do with the performance you get at a given power level.
Voltages and currents are easy to measure relatively precisely.
Interestingly, that recommendation could be interpreted "empirical studies based on averaged node performance" give a very distorted view on "the true impact of manufacturing variation on processors".
It's an interesting set of measurements, but the assumed source of the variation is dubious, and it's not clearly what, if any, actions it really supports.