Intel Has PCIe 4.0 Optane SSDs Ready, but Nothing to Plug Them Into
tomshardware.com
tomshardware.com
What's the business dynamic of Intel like? Would they be fine with customers using them with AMD CPUs or would they delay the product?
Seems like it only works with Intel 7th gen and later.
Although there's a post on the LTT forums[0] exclaiming that Wendell managed to get it working. (although he also got Thunderbolt working before on AMD)
[0]: https://linustechtips.com/main/topic/961841-we-ran-intel-opt...
NVMe Optane as a product just shows up as a small, fast drive. StoreMI works with it, even faster than Intel's stuff in some cases.
There's Optane memory, which is the one the link is referring to, it needs Intel CPUs
Then there's Optane SSDs, which works with AMD fine
Source: I'm using them on EPYC servers
Optane memory is not a traditional SSD, it's more of a disk cache, matched to the Intel CPU. While the rest of the Optane family are standard SSDs
If you follow Intel's marketing "Optane Memory" refers to the SSDs. The Optane DIMMs are called "Optane DC Persistent Memory".
The natural things to call them are "Optane drives" and "Optane memory". Don't criss-cross that!
It's a little confusing because Intel markets "Optane" as so many different things. "Optane" as marketed to the consumer is a combination of an Optane NVMe drive and motherboard-level support for disk caching. However, if you choose not to use the caching software, it just turns into a SSD.
The only catch is that most optane drives are pretty small. The consumer ones intended for cache are about 16GB. However, you can buy bigger ones up to about 120GB in M.2 format, and PCIe or U.2 based ones up to 1.5 TB aimed at the prosumer market.
AMD actually does really well with these because they have an extra x4 PCIe lanes (16+4 + 4 more for chipset) so you can run a graphics card at x16 speed and still have 4 more CPU-direct lanes for an Optane drive.
Then on servers you have Optane DIMMs which sorta-not-really replace RAM for massive in-memory servers.
I don't imagine PCIe 4.0 will make much difference as a single drive can't make use of the extra bandwidth anyway - but I'm curious to see if there are improvements to the 3D XPoint memory. Kinda bummed I literally just bought mine.
With the speed of current SMP interconnects, making the chipset completely off-package again is possible, but I don't see the interest.
Somehow they are owned by the same parent as Anandtech, which has gone downhill, is still readable. It's not total spam like Toms, even if I miss their in-depth Mac articles.
I wouldn't get on my high horses about that, it's commonplace nowadays that former commercial media outlets have become "infomercial" businesses, essentially marketing agencies disguised as news/information outlets. The primary drive being that consumers of media don't bring enough revenue, whereas announcers and brands do, often shadily in this "new media" environment (undisclosed sponsorships, etc).
What you describe is, as I see it, just the rotten tip of Tom's iceberg.
Like you — and I know it may be biased — I tend to "identify" potential "red flags" just this way: rotten website (technically, cue Js) probably means shady business behind, in my book. Otherwise, why would you disingenuously break UX like that? Forbes comes to mind as an offender, and so many other formerly big names of the press. Just gone, in spirit and content, as of this century.
Worth noting afaik, Tom himself (the founder) sold and left a long time ago now (probably chilling on some tropical beach with his spouse and kids? I wish him so).
[1]: https://www.tomshardware.com/news/nvidia-rtx-gpus-worth-the-...
[2]: one (funny) rebuke by GamersNexus, a trustworthy technical media: https://www.youtube.com/watch?v=tu7pxJXBBn8
You could potentially put a 4.0 chipset on a 3.0 chip and it should nominally work, the chipset would provide 4.0 lanes to devices, but all the traffic would be multiplexed at 3.0 to go back to the chip so there wouldn't be a whole lot of point.
You could also put a 3.0 chipset on a 4.0 chip, which works fine and is even sensible for budget motherboards (this is how the AMD B550 chipset will work).
The things on the chipset tend to be slower devices that just need to be attached, not necessarily run fast. The chipset usually only gets 4 lanes total (so like, one NVMe drive saturates it) and hopping to the chipset adds latency which reduces IOPS on fast networking or Optane drives, reduces graphics performance for chipset-attached GPUs, etc.
[1] https://www.tomshardware.com/news/intel-stratix-10-dx-upi-cx...
Nominally QPI/UPI but those protocols are not hugely distinct from PCIe in general. AFAIK it’s basically PCIe but encrypted, so that nobody else can replicate their chipsets (like used to happen in the old days with nForce/etc).
Also your numbers are off, easy rule of thumb is that one PCIe 3.0 lane is one GB/s of bandwidth per lane. So 3.0x16 is 16 GB/s of bandwidth.
So it just needs 8 GB/s of bandwidth to run at 4.0x4 speeds.
On HEDT and modern server, (2066 and friends), only about 8 of the PCI-E lanes come from the chipset, and the rest come directly from the CPU. The QPI and it's successor UPI is used to connect CPUs to each other, not to a chipset.
Consumer workload see little to zero measurable benefits. Once you pass a certain Random Rd / Write speed, Seq Rd Write is still king, or likely not the source of bottlenecked.
[1] https://www.servethehome.com/intel-optane-hands-on-real-worl...
[2] https://research.fb.com/wp-content/uploads/2018/03/reducing-...
https://www.phoronix.com/scan.php?page=article&item=intel-op...
If that's not relevant though, how would you benchmark compilation and disk caching for IDE? I could perhaps try it myself...
One possible way to test this out is if you have enough RAM and just fit everything inside a RAM drive, basically removing all I/O speed concern and see if there are any significant improvement.
After all, if you have to wait 100 microseconds per 4K read, a single thread can only utilize 40 megabytes per second.
Scroll down and you'll see a graph comparing latency and IOPS for a 4kB 70/30 read/write workload on Alderstream (the codename for the 2nd gen Optane SSD), a NAND SSD (P4610) and the current Optane SSD (P4800X). It's just a snapshot for now, but I'm sure more is coming.
The Optane benches 3x faster on low queue depth 4k random reads. 4k writes are comparable. The Evo Plus beats the Optane by under 10% on deep queue 4k reads and writes and like 15-20% on sequential reads and writes.
[0] https://www.techspot.com/review/1893-pcie-4-vs-pcie-3-ssd/
https://www.macrumors.com/2020/01/06/intel-5ghz-comet-lake-c...
Here's an intel product to plug them into already today: https://www.anandtech.com/show/14906/intel-ships-stratix-10-...
And there's also AMD x86 processors that support it.
Intel's FPGAs aren't x86 chips, especially when their FPGAs just came out of an acquisition. It's a rebadged Altera.
>Given that Intel doesn’t have any processors (aside from the Stratix 10 FPGAs) that support the PCIe 4.0 interface, the developers obviously don't have access to an Intel-driven test platform with the new interface
Beyond that, Stratix 10 is "shipping" in the sense that low-volume samples are being distributed to large partners, but it is practically impossible for anyone to buy a Stratix 10 in any formfactor other than dev kits.
And the non-$10,000 dev kits don't have PCIe 4.0.
The article is obviously about the lag Intel is experiencing with getting PCIe 4.0-capable products to the larger market.
You can get Zen 2 and POWER systems with PCIe 4.0 today, and it is highly likely that ARM-based motherboards supporting PCIe 4.0 will be available on the general market for actual purchase before Intel releases something.
One-offs, samples, test gear, and dev kits don't "count".
If they did, then PCIe 4.0 was first "available" in early 2016 because engineers got their first PLDA dev kits which allowed them to start prototyping their designs.