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Comment by Animats | Hacker News Reader

At some point the semiconductor industry may hit a limit on size because it costs too much. TSMC is planning a massive new fab for the 5nm and 3nm nodes, with an estimated cost of $16B. Everything at the latest node sizes is insanely complicated and expensive - fabs, masks, design. I'm amazed that generating extreme ultraviolet by zapping falling tin droplets with lasers can be made into a cost-effective production process. Mask costs passed $15 million at the previous node. Design costs for 7nm are around $100 million for each different part.

This can't go on much longer. Most of these parts go into phones.

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No, but the cost per transistor can keep dropping for years after shrinkage stops. Look at a lot of other things like TVs where competition keeps driving the price down. Unless something new comes up that practically everybody wants, competition will drive down prices and profitability.

I feel like we’re on a path with technology where our expectations of advancement have us using ridiculous “should have only been a prototype” tricks to get things done, where giving us just a few more years would get us far cheaper and more stable approaches to the same processes. (Analogy: it feels as if, upon the invention of radiotelegraphy, we wanted higher throughput, and therefore we just figured out some ridiculous way to trigger off pipelined arrays of spark-gap transmitters, rather than inventing vacuum tubes.)

Some foundries have purposely held back on scaling improvements, precisely because the older, coarser processes can still find a lot of use and be optimized in other ways. One can also see Intel's iterative improvements on their 14nm++++ process in the same vein.

There was much hope that somebody would find a way to create an extreme ultraviolet light source that wasn't the size of a house and costs over $100 million. There's a startup in Fremont CA trying.[1] "A synchrotron beamline for home laboratory applications", says their site. (That appears to be humor; the thing costs about $30 million.) Right now they have a product for imaging but can't generate a powerful enough beam for lithography. They may be funding-limited. It took them 19 years to get to this point. Worth a look by VCs with $100M+ to invest.

[1] https://lynceantech.com/

> Mask costs passed $15 million at the previous node.

If I'm interpreting/understanding you correctly, that means chip simulation is worth some multiple of $15m.

I am very very very very very curious what that buys in terms of chip-scale simulation. Obviously a perhaps tricky question because the answer would be so specific.

But I still wonder at least what it would look like from a distance. A massively parallel server farm that collectively pretends to be a 100MHz(??) chip? FPGAs? Custom silicon that has microcode-on-steroids?

Photolithography masks, see https://en.wikipedia.org/wiki/Photomask.

Simulation is massively used in chip design these days. The hardware they use is just the cheapest general purpose compute hardware available, so just normal server/hpc setups, so this guess was pretty close:

> A massively parallel server farm that collectively pretends to be a 100MHz(??) chip?

... except that you are greatly overestimating the speed at which such simulation can run. The full-chip silicon-level simulations ran on massive datacenters run at speeds measured in kHz, not MHz. For the kind of testing they are used, this isn't a major detriment, as so long as all the io is slowed down to match, they can still get an accurate results, they just take a bit longer.

A lot more simulation happens at the subsystem-level. You can isolate some subsystem, such as a cache controller, and then manufacture traces of the communication it does with the rest of the chip. Then you can just simulate that part at much lower cost, do tweaks, see how the operation changes under the simulation, and repeat.

> kHz, not MHz

Ha, I overestimated the capabilities of scaleout :D I figured if you added enough racks you could go that high... but yeah, that's asking for the equivalent of total coherency on a piece of software running simultaneously across thousands(?) of nodes.

(Ha, I wonder if the current systems use 50Gbit networking. Or 100Gbit? Wow...)

> A lot more simulation happens at the subsystem-level. You can isolate some subsystem, such as a cache controller, and then manufacture traces of the communication it does with the rest of the chip. Then you can just simulate that part at much lower cost, do tweaks, see how the operation changes under the simulation, and repeat.

Right, that makes sense. And interestingly, that sounds similar to how retro/hobbyist emulation systems do things too. Emulate the exact behavior necessary for a specific set of things to work the way you want.

> I figured if you added enough racks you could go that high... but yeah, that's asking for the equivalent of total coherency on a piece of software running simultaneously across thousands(?) of nodes.

Also, you've got hundreds of users, who may be submitting tens of tests at a time. Like, even a giant company would run out of compute trying to make simulation as fast as the users want it to be.

Cisco will gladly sell you 400 gigabit switches: https://www.cisco.com/c/en/us/solutions/data-center/high-cap...

> For the kind of testing they are used, this isn't a major detriment

Eh... 1 hour tests turning into 4 hour tests turning into 12 hour tests is one thing, but when a 12 hour test turns into a 7 day it hurts. And if a 20 day long bootloader simulation with accurate pad models fails, you may not have a chance to run it again with a fix before tapeout. And Kernel boot in simulation takes so long.

Not that you're wrong, just emphasizing how slow it can be. Simulation complexity has outpaced server farm speed increases over the past 10 years, in my experience. And rtl simulation has slowed itself out of usefulness for many software use cases where it used to be not so bad.

$16B is about $1/device, under $10/end-user. Not a lot of money at scale.

Forward looking is about 6k$ per wafer. There are 100 fields, and 8 devices per field (at 100mm2). So, about $10. Assume 80pct yield, and we are at a minimum of $12.

16B$ is 1m wafers per year for a foundry. About 7B in litho tools, 2B in dep, 1B in CMP, 5B in etch, and 1B in I&M. I am assuming about 70 litho layers, EUV moderate, significant double patterning.

Anyway, I don't see a way for $1 for any useful sized device at forward looking nodes. That is why the ecosystem needs apple, quallcomm and Nvidia to push performance on the early end.

This is a huge deal if you have a failed fab, look at Intels current situation.

$16B is about half of TSMC's total yearly revenue. Now factor in the fact that you need a new >$16B fab in <2 years.

There's a reason why there is a shortage of semiconductor fabrication capacity.

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