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Yeah, if you just replaced the 64KB of RAM with a 4KB cache backed by DRAM, you could probably fit 64 cores in one of those no problem, but 1) the performance wouldn't be quite as good, and 2) this project was mostly an exercise in excess since I was trying to find something to do with my giant FPGA board.

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Sorry, to be clear, that was by no means a criticism of what you did. I was just pointing out that this kind of thing is more accessible to people than they may think when they get sticker shock re: the cost of that particular FPGA you built on.

I'm guessing that simple one-way ring IPC mechanism is going to be a bottleneck in a hurry as you add more processors.

It's current manifestation is very much a 'good enough' solution. I just wanted a scheme for simple all-to-all connectivity to map the serial ports to, and the only traffic it carries at the moment is either terminal traffic or disk data from the SD card, so it's not even close to being taxed. The obvious improvements are to add deep buffers to hide the latency of credit return, crank up the clock and to make the bus wider. This board could probably handle a 200-bit wide bus at 100 MHz+ speeds with no problems. Computer architecture is a fun hobby =)

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