One Instruction Set Computer | Hacker News Reader

One Instruction Set Computer

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54 pointslelf26 comments

So like x86 mov?

https://github.com/xoreaxeaxeax/movfuscator

Except you wouldn't actually need to store the opcode for the instruction.

x86's version of a single "instruction" is frequently a large class of opcodes. It's kind of crazy considering the assembler chooses one of the following numbers for "mov" based on the operand types, not the mnemonic:

    88, 89, 8A, 8B, 8C, 8E, A0, A1, A2, A3, B0, B8, C6, C7

This also ignores all of the prefix bytes.

https://www.felixcloutier.com/x86/mov

Also, MOV is far from only a bit copy. It's (potentially, depending on the operands), left shift, add, load, store.

Came in to mention that, but the crazy stuff I was thinking about is surprisingly not mentioned in the main readme. Behold:

https://github.com/xoreaxeaxeax/movfuscator/blob/master/vali...

Yes, Doom running with just MOV.

That's pretty amazing

“Running” might not be the best word for it: “The mov-only DOOM renders approximately one frame every 7 hours” I.e. about 0.00004 FPS.

Transport Triggered Architecture seems not only isomorphic but essentially equivalent to a conventional architecture if you notice it is effectively just relocating/packing the opcode bits into the operands. This seems to be an implementation detail of the hardware (which bits does it gather opcodes from) and not an essential difference in the ISA. Am I missing something?

If you had a writable control store then yes. But most processors these days don’t expose that API.

A thread from 2015: https://news.ycombinator.com/item?id=9388137

2011: https://news.ycombinator.com/item?id=3046980

Semi-related, I just learned about this 1-bit microprocessor the other day: https://en.m.wikipedia.org/wiki/Motorola_MC14500B

Daniel Hillis’ famed Connection Machine architecture (until the radically revised CM-5) featured hypercube-geometry “one-bit processors” which were really “definable logic gates”.

This is good, although I study esoteric programming so have known a few of these things.

I have also once designed a schematic for a transport triggered architecture without knowing that it was called that; I just had the same idea. (But, many people will have similar ideas, and not always know what it is called.)

TOGA computer is like a presettable binary counter, NOT gate, memory, some logic for timing (so that it does not interfere with itself), and not much else.

But what is not mentioned is Muxcomp, which is something I am much more interested in, and is also with only one instruction. (Although, I thought of using it as part of a user-programmable VLIW microcode.)

Every example under "Instruction types" looks like a combination of 2 (or more) instructions. "Do this AND do that".

Of course, taken to the logical extreme we can have the "RISC OISC", which is just an instruction that interprets the operand as a fixed-width instruction for a RISC architecture ;)

Whether something does one or several things largely depends on your perspective. You might think of ADD as a single instruction, but it fiddles with a lot of bits...

This is "one instruction" in a sense of having only a single opcode.

I’ve just recently started looking into implementing a minimal ALU, and I’ve been having trouble finding good resources to answer the question “other than a one-instruction computer, what is the smallest number of instructions needed in a Turing-complete RISC?”

I’m guessing it would be NAND, ADD, increment, and some sort of branch?

NAND covers all of the bitwise ops. If you have ADD, NOT and increment, you can get SUB. If you have ADD and SUB, you can get MUL and DIV.

Am I missing anything?

I don't mean this the wrong way, but since you know one instruction is sufficient, the next smallest number is two. Maybe by RISC, you meant a small orthogonal set? Load/Store/ALU ops separated? So ADD and NAND work on registers with transfers using LOAD and STORE? Seems like you'd need a branch, unless the instruction pointer was one of your registers.

Brainfuck has 8 ops, 2 of which are for input and output. It's Turing complete, and the operations are super simple, but I'm not sure it's RISC-ish.

https://en.wikipedia.org/wiki/Brainfuck#Commands

You can build ADD and INC from NAND.

This (educational) ISA has just NAND and ADD: https://user.eng.umd.edu/~blj/RiSC/RiSC-isa.pdf

Exactly what I was looking for, thanks so much!

Is this the era of microcomputers like we have microservices?

that word already means something, and it describes probably every computer you’ve used in your life. so... yes? but the era of microcomputers started in 1974

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