Since there is some curiosity around temperature and voltage variation - here are some more details for you folks to geek out on.
When you build a system with a DRAM interface, you typically specify 2 parameters - A temperature range you guarantee its operation within. For example, this range could be 0C-80C. - Maximum rate of change of temperature your system can handle. Example, +/-2C/min.
Now, to test if the system can withstand the above 2 parameters, while the firmware is being developed it is put in a Thermal Chamber and experiments such this are conducted: - Do a cold soak for a few hours (i.e., power down the system and leave it in a 0C chamber for a few hours). - Then power on the system and let the DRAM interface calibrate at this low temp - Then start a stress test which reads and writes to the memory, and simultaneously ramp up the temperature of the chamber at the specified rate upto your maximum (2C/min upto 80C in our example here) - If the test fails, it typically means the signal integrity is not good enough. Then you go back to the lab, probe the DRAM interface and observe the signals on an oscilloscope (if you have to). Then re-calculate/fiddle around with 6 parameters until you have it all working. These parameters are 1. The drive strength of transistors at the Processor when its writing data to memory 2. The termination resistance of the transistors at the Processor when it is Reading data back from memory 3. Voltage reference (Vref) - This is the value the PHY[++] uses to decide if a voltage level is a binary-0 or 1 4. The set of 3 parameters above exist on the DRAMs as well. Making it a total of 6.
It is easy to imagine what drive strength and termination of transistors mean. But Vref is a bit more interesting.
In DDR4, binary-1 is represented by a 1.2V signal, but binary-0 is a floating voltage value. It could be 0.2V or 0.4V, or whatever. It depends on the termination at either end of the PCB trace. This type of a circuit is called POD (Pseudo Open Drain). Since the level of binary-0 is variable, the DDR controller calibration logic has to figure out where to place Vref so it can reliably decode 1s and 0s.
Lastly, just like the cold soak experiment, we also do hot-soaks with a ramp down and several other modalities to ensure the system is solid.
The PHY has delay registers within it which you can read to figure out the result of calibration. When you power on a system after a cold-soak vs a hot-soak, you'll see different values in these delay registers.
PHYs these days are very robust. They typically don't need periodic calibration (re-tuning of delay registers) while operating in a typical data center environment. Of course, it's a different story if the system if sitting somewhere off on an oil rig.
— [++] The PHY is separate from the DDR controller. This is the actual analog circuits at the edge of the processor sending out and receiving signals on the PCB.