That information simply isn't captured in current schematic software. Until it is I can't see autorouters being effective.
I can see a world where every schematic includes simulation models, and the autorouter uses simulation data to know exactly what frequencies are moving down each net and in each location. That requires detailed spice models of every component on your circuit though - so it probably wouldn't save the designer any time anyway as they're just doing different work. I'm not even sure how you'd simulate the signals coming out of a microcontroller - how does the autorouter know that one PWM IO is producing a 500kHz clock into a high current switch and the other PWM IO is producing a fixed 3.3V?
So then maybe you need to incorporate not only simulation models, but your actual CPU code. Which then means you need high quality microcontroller and FPGA emulators. There's a new problem!
There's probably a middle ground - a designer could annotate each net with a waveform which would be fed into the spice simulation - but even then we're talking significantly more work than just laying it out yourself.
Have a test where a specific pin on the processor is set to a 500 kHz and have tests for certain conditions, emissions below a certain level, interference with some other trace, etc.
Everything with hardware development seems to be at the stage of a neglected codebase with manual testing, poor test coverage, and slow process. We're just at the point where many of those problems are solvable now with pretty good actual EM simulation.
Lots of features need to be added but it all just seems very possible at this point.
https://en.wikipedia.org/wiki/Profile-guided_optimization
https://en.wikipedia.org/wiki/Sensitivity_analysis
https://en.wikipedia.org/wiki/Fixed-point_iteration