Aw, I was hoping the explanation would be in the thread. Is it high-frequency noise from an unshielded clock? Surpassing a current or temperature limit due to the stress of the high resolution and resulting high memory bandwidth? Time will tell!
I bet that's it.
2560x1440 @ 60 Hz with CVT-RB timings has a pixel clock of 241.5 MHz. The TMDS bit rate is 10x the pixel clock, and 2415 MHz is right in the lower end of the 802.11 band.
If the Pi can be convinced to use CVT blanking, that'll raise the pixel clock to 312 MHz, which should be fine.
Not an electrical engineer: which measures are usually adapted to handle termination issues?
https://tomverbeure.github.io/video_timings_calculator
Changing the refresh rate would work too, but some monitors can be pretty picky about that.
Forcing a different pixel clock is probably the easiest fix, and since the ports claim to do 4kp60, that should be possible (if the display supports it).
Now the question is who screwed up. Is it a leaky cable? Is it bad PCB design? Is it a problem internal to the SoC? Is it a power delivery issue? Knowing the RPi foundation and Broadcom, I bet one of them screwed this up for all RPis and it isn't just a bad cable.