[2] https://www.freecadweb.org/
[4] http://www.geda-project.org/
[5] http://www.clifford.at/yosys/
[6] https://symbiflow.github.io/
[7] https://www.chisel-lang.org/
It's not really like programming. The tools are deeply integrated into the physics of the system.
What specifically makes electronics different from modeling other systems with software? DSP immediately comes to mind as something that is explicitly tied to Maxwell but there is really good software out there for describing, modeling, and creating signal processing components similar to how you'd write software. An example of this could be GNU Radio.
Is there something that prevents the creation of workflow automation tools, abstractions, and "compilers"/DSLs?
Do engineers at Intel, AMD, and Nvidia manually lay out each feature in their chip designs? If not, what workflow tools have they developed internally? Could those tools, or similar, be used for smaller scale circuit design?
As for the DSLs/workflow/etc there are companies in this space.
The answer is yes, but of course not exclusively. There was an English talk at ccc a while ago by an AMD engineer with lots of details on the whole process.
https://github.com/verilog-to-routing/vtr-verilog-to-routing
KiCad (funded by CERN) and LibreCAD are pretty good PCB layout and routing tools. Since Autodesk bought Eagle, they're the Open Source "great hopes."
For PCB tools, you should just join an existing project since there's several Open Source ones and we need better ones, not more. This is a suitable long-term hobby if you occasionally make boards yourself. Especially welcome if you work on the parts library UI and items.
Chisel, etc. are hardware compiler tools, not board layout tools.
You should get a job at a chip or HFT company and have them pay you to learn and apply this stuff.
The commercial software is shitty since the vendors spend more on keeping their license dongles up-to-date than adding features.
Source: worked at a company that designed a 400 million transistor chip. Most of my X-co-workers worked on the A11 and A12.
And a lot of the tools you mentioned are targeted towards FPGA design rather than full or semi-custom ASIC design. The big three have tools that can handle both.
And let’s not forget “EDA software” was single handedly pioneered by one woman and some lisp. Before then, it was hundreds of men taping out circuits on 4x8’ ply with...physical tape who all complained the labor and complexity costs were enormous and nothing could be done.
If we really want to point fingers, we could say it’s a monopoly on the supply chain side of manufacturing - costing millions in NRE’s to make a chip - but if you are willing to scrimp on process size you can get it done for $3 per layer per reticle at 500nm scale and $50 per mask.
I would try the local university with an electronics program.