FPGAs that speak your language

God I'm so tired of the same article over and over again. Firstly, if you want to claim you can programme an FPGA with a high level language, you have to exclude languages that are just syntactical sugar over hand coded RTL like Maxeler does. Secondly, you don't get to wave your hands and go "Oh, the high speed interfaces are done in RTL still" - well yeah, because that's an actual difficult performance problem and we know HLS can't do that.

You also have to answer why you're tackling why you're doing this work on an FPGA at all. Yes, you can do ML on FPGA - mainly because the FPGA companies are tripping over themselves to get some of that market. But that's offline analysis, so there's absolutely no reason you can't do it on a GPU - which is probably going to perform a hell of a lot better, let you iterate on a design in minutes not hours, and uses real high level languages including actual ML frameworks.

>Development time can be cut significantly, while maintaining latency and resource usage at a similar level to hand-crafted FPGA code

Here's the key. I've seen development time cut by using HLS. I've seen HLS designs with similar latency and resource usage as hand-crafted code. I've never seen those two together. You either get designs that are orders of magnitude worse than hand-crafted RTL but were quick to design. In which case, ask yourself why you're shelling out for an FPGA when you probably could've used a GPU. Or you do a first draft quickly, but to get to high performance you end up basically fighting against the tool until you've forced it to generate the RTL you could've written in half the time.