IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic Interface | Hacker News Reader

IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic Interface

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79 pointsrbanffy41 comments

IBM has solved another fundamental problem before most are aware of them, the other CPUs are hitting a memory and interconnect wall. If you're paying attention, this has been the norm for POWER since its inception. It's too bad the OpenPOWER stuff has been underused. It's really good stuff.

With the exception of talos and various bits of used hardware POWER has only been available in rather expensive systems-- so no onramp.

Even with things this announced it remains the case that EPYC, not power9, is the king of memory bandwidth per dollar at least at most price-points.

> at most price-points

Worth noting POWER9 reaches price points (and profit margins) EPYC server vendors can only dream of.

Sadly, you are right about onboarding. I'd love to have a POWER9 box as my desktop workstation, but I simply can't justify the price compared to a beefy Xeon (or EPYC) box. IBM would be wise to have a POWER9 that could compete with low-end Xeon servers.

Indeed, there is a realm of astronomical hardware that is covered by power9 that you're not finding amd hardware for, but going down to "merely the price of a new car" and below is where the comparison falls apart.

And the astronomical end really only matters if you need special requirements like single system images... if you just need lots of cycles or memory bandwidth, a cluster of lower end hosts (and 40GBE nics) is a lot less pricey.

> a POWER9 that could compete with low-end Xeon servers.

The Talos II is in the vague order of magnitude for that... which is A LOT better than before it existed.

True, but it's still, sadly, above my impulse-buy limit.

To make things a bit harder, I live in Europe and there aren't as many sources of used POWER8+ gear as there are in North America.

That's in recent years, of course. Previously, POWER was the architecture for Apple computers, as well as the Sony PlayStation 3.

I had a PS3 for building for power/cell... until sony bricked the darn thing! :)

After that for a while my PPC test box was a dual g4 xserve but it stopped booting inexplicably.

I have talos now and am pretty happy with it, but even that still struggles to compete with epyc in terms of price/performance (though at least a comparison can be made there).

I have some memories of the Cell processor, none of them fond. That beast was the hardest thing to program I ever saw. It made the first generation Xeon Phi's look like a dream.

I think it just depended on what you were doing on it, I 'ported' the CELT (Opus predecessor) to it in like.. an afternoon.

If you really want what POWER has to offer, like the ability to explore low level board firmware, the price is extremely competitive.

IBM has been doing this for years.... at this point, research has to be a huge part of their expenses and royalties a huge part of their revenue. They invented things like copper interconnects that are standard now, along with a huge raft of other fundamental computing technologies still in use.

If IBM ever loses its technical edge and research staff, it's going to go under.

I had been reading about speeding up game programs by taking advantage of cache lines. Also, I've been reading "IBM's 360 and Early 370 Systems" and came upon the initial development of cache. You'd think that the initial cache would fetch and store a word, but it didn't. It grabbed a block of words. In other words, a cache line. In 1968.

> Compared to the standard direct-attached DDR4, with an OMI DDR4 DIMM, you are looking at triple to quadruple the bandwidth at the cost of 5-10 ns higher load-to-use than RDIMM.

It would be interesting to see benchmarks on the impact.

> at triple to quadruple the bandwidth at the cost of 5-10 ns higher load-to-use

You need to make full use of the bandwidth for this to be an overall win.

Once you use more than 75% of the available DRAM bandwidth, things start to get wonky, with large unpredictable CPU spikes, as the CPU stalls increase. So I think you'd see a definite benefit if you use more than 75% of the available bandwidth.

We (Netflix CDN) are currently bandwidth limited for serving TLS encrypted video using software ktls. (~100Gb/s on broadwell, 150-160Gb/s on skylake/cascade lake, 220Gb/s on EPYC Rome). So I'd love to have twice the bandwidth. With twice the bandwidth, I think we could probably serve 400Gb/s from a single Rome based box.

Note that I'm also looking forward to trying new kTLS offload NICs that should cut the bandwidth requirements.. those are a much more viable short-term path forward.

Wow. What kind of networking hardware do you push to/through? I have a hard time visualizing where/how you would "put" 200 gbps worth of data over (any) network...

There is a presentation from EuroBSDCon 2019, that describes the techniques and hardware used to achieve that figure [0].

There is also a thread in HN if you're interested [1].

[0] https://people.freebsd.org/~gallatin/talks/euro2019.pdf

[1] https://news.ycombinator.com/item?id=21043765

Multiple Mellanox or Chelsio 100GbE NICs in an LACP bundle.

The 220g is from a prototype with a Rome CPU in a Naples-designed motherboard, with 4 Mellanox ConnectX-4 100GbE NICs. 2 of them are limited to Gen 3 x8 (since it is a Naples generation mobo).

I'm curious about you being limited to 220 Gb/s on an AMD Rome box. The maximum theoretical DDR4 bandwidth on such a system with 3200 MT DDR4 is 204 GiB/s, so you'd only be using ~15% of the DRAM bandwidth assuming the block/record/file size of the cached data you're serving is enough to mask the DRAM latency.

as to where, is internet infrastructure this bad in US? Even something like 35C3 had 500gbit pipe last year https://media.ccc.de/v/35c3-9576-35c3_infrastructure_review

No, the US is one of the most densely connected countries in the world. Fiber was over-provisioned by the functional Bell monopoly, railroads, and a smattering of upstarts in the 1980s and massive infrastructure capital bubble in the 2000 dotcom crash which was more about this infrastructure than software or computer hardware.

If you hear people in the US complaining about their internet connection, it is because the local duopoly of telephone and cable company is failing them. In terms of industrial fiber, the competition is fierce and you can light up Nx100G to almost anywhere in the country.

The industrial fiber capacity is fantastic here. What sucks is the consumer internet service. In most places in the US, there is a monopoly/duopoly for consumer ISPs and they certainly abuse their positions.

Wow, you still handle TLS in software?

I worked on a few CDN projects, and on a DC project for Alibaba. Even in 2013, I think, all big CDNs used Intel hardware accelerators.

The beauty of this approach is that if you need more TLS bandwidth, you just plug more TLS cards, and you are done.

Otherwise, it's impressive to see how much TLS throughput people can get on CPUs today. Back in 2013, the best accelerator was only able to pull like 30Gb/s per card

How much are the accelerators? something tells me more expensive than delivering comparable throughput, highly flexible off the shelf x86 hardware.

You're also not tied to any particular vendor with a pure software approach.

Realistically with something well-defined like TLS you use a library that supports pure software or hardware acceleration. Then you can use acceleration without any lock-in.

Back in 2013, Intel 8920 did cost $750 wholesale, and similar Broadcom card a little bit cheaper.

Looks a lot now, but back then you didn't have server CPUs with gazillion cores on the cheap.

It was also about getting more bandwidth to a single server. 20Gb/s was a practical limit per mainstream server, but with accelerators you could've multiplied it many times more than the fastest CPU on the market.

> Looks a lot now, but back then you didn't have server CPUs with gazillion cores on the cheap.

You also didn't have the AES instruction set to improve the SSL performance.

Intel hardware accelerators sit on the PCIe bus, and burn just as much memory bandwidth as software encryption. The dataflow is basically:

  - disk DMA writes page from disk into DRAM
  - CPU (or PCIe crypto accel DMA) reads page from DRAM
  - CPU (or PCIe crypto accel DMA) writes encrypted page to DRAM
  - NIC DMA reads encrypted page from DRAM

Nothing changes from a memory bandwidth standpoint if its the CPU or a PCIE device doing those middle 2 steps. With "NIC TLS" (eg, inline hardware TLS) accelerators that sit on the NIC, those 2 middle steps can be eliminated, and condensed to the pre-crypto dataflow

   - disk DMA writes page from disk to DRAM
   - NIC DMA reads page from DRAM to NIC

That's wonderful, I and wish we had those things years ago.

Back then it was a realm of custom FPGA setups with very few niches like digital TV broadcasting, or expensive VPN appliances.

Ideally, I would've liked it a lot if the NIC could've spoken directly with the raid card or NVME using PCIE P2P... dreaming too big

> We (Netflix CDN) are currently bandwidth limited for serving TLS encrypted video using software ktls. (~100Gb/s on broadwell, 150-160Gb/s on skylake/cascade lake, 220Gb/s on EPYC Rome). So I'd love to have twice the bandwidth. With twice the bandwidth, I think we could probably serve 400Gb/s from a single Rome based box.

When I commented, I was assuming that people would be moving memory from RAM to the CPU to do something useful with it. If you are just dumping memory to the network, it would be more efficient to skip moving the memory to the CPU all together, or to even skip a normal CPU completely and just have network cards with a lot of RAM.

10 years ago, when AMD moved high speed memory controller to the CPU, it was lauded the best thing since the sliced bread.

Now, 10 years later, we again move memory controller off the CPU.

Things change. What made sense 10 years ago in PCs and midrange x86 servers doesn't currently make much sense on the higher end of the POWER9 spectrum.

really only because one company has a patent portfolio sitting on the entire notion of dram asynch serial interfaces. i think* those should start expiring soon

> Centaur memory buffer chip

Any relation to Centaur Technologies?

Doesn't look like it. The Centaur is described as "a memory buffer chip designed by IBM for their POWER scale-up microprocessors" while VIA owned Centaur's website seems to have gone from "tune in for a massive unveiling later this year" a few years ago to what looks like a promotional leaflet for student and internship programs. I guess they mostly do research stuff now and very unlikely to design stuff like this for IBM.

Zhaoxin has taken over distribution (and possibly some of the development) of the Centaur designs. Centaur has over 100 employees listed on Linkedin, so I think they have been working quietly for many years.

https://en.wikipedia.org/wiki/Zhaoxin

https://www.tomshardware.com/news/china-zhaoxin-kx-6000-core...

I assume they are still an important player in the embedded x86 niche. When I worked on the Brazilian voting machines, we were using Via CPUS.

The problem is as far as anyone can tell they are living off the same designs they had a decade ago and not actually coming up with anything new. None of those designs are actually able to compete in any segment these days: not performance, not low power, not performance/W. Unless they can somehow be the absolute cheapest option and go for the segment where anything is good enough it's hard to see them make a living, let alone thrive and come up with something new.

Those chips are vaporware, they dont exist

"as I posted under https://news.ycombinator.com/item?id=20238207 you wont be able to buy them full stop. They are samples (if they ever existed at all). Afaik not a single device shipped with those CPUs ever. They are the product of: "National IC Investment Fund (called the "Big Fund") will mainly focus on three key sectors in the coming years, including memory, SiC/GaN compound semiconductor, and IC design with its application in IoT, 5G, AI, smart vehicles, etc." ~$75 billion by 2017

https://press.trendforce.com/node/view/3025.html direct non-repayable cash money funds up for grabs to anyone showing something on paper."

Look at this roadmap http://app.semi.org.cn/data/resource/Image/qq2(1).jpg Do you remember that 4 core 2GHz Via cpu from 2015? or maybe that 4/8 core 2017 one? None of them ever existed.

It looks like Centaur as such has very little left to offer except as a research and educational platform. They sold a design (Isaiah core) to a Chinese company so they can manufacture a very low performance x86 CPU as an alternative to Intel/AMD in case the US ever bans exporting this to China.

But there's certainly nothing new coming out of Centaur or Zhaoxin except the rehashed versions of the CPU above. And that may not be enough for either since now China also has access to AMD's Zen core [0].

[0] https://en.wikipedia.org/wiki/AMD%E2%80%93Chinese_joint_vent...

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