TSMC 5-Nanometer Update
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I do agree that it is frustrating for someone from the outside to understand exactly what kind of scaling one can expect.
Data centers get cheap bulk power, cooling is mostly passive now (evaporative) and backup power systems are also a lot cheaper now compared to the compute cost than in the past.
Who knows, perhaps even Intel will use TSMC's process at some point.
(I'm assuming that Intel doesn't allow competitors to use their fabs; and that Intel does indeed have the best fab-tech at the moment; maybe I'm wrong.)
The problem is that the paradigm shift technology we've read about multiple times has always been overcome by more investment in standard silicon processes.
Economically we're long past the point of contraction - there has been a ridiculous pace of mergers in the semiconductor industry to have the network effects to stay current. The effects are worse at the top, and we are down to three companies even in the race.
Basically, no, we'll never have another fab entrant who is a major player.
That said, in a lot of ways the really interesting stuff is likely to happen on the older nodes. There's really nothing enabling about the latest fab node... it's just bragging rights for the highest absolute performance and/or performance per watt for CPUs which most applications don't need and can't afford. ARM/RISC-V/whatever doesn't need 5nm to be feasible... in fact, those 'other' products often aren't viable on the latest nodes due to cost unless you're a market leader with huge volumes to amortize the cost over.
[1] Sure, they still offer the absolute top performance per thread... by a bit. But look at the price they're paying from a perf/watt standpoint to get there. I seem to recall AMD being ridiculed not too many years ago for doing this...
Doubt it. There are only two players in the x86 market.
I haven't seen anything compelling for personal computer and server space yet to take over AMD or Intel. I believe AMD is going to gain some market share with their new products.
A quick search didn't bring anything.
They are just saying that for the same power usage as previous tech, they get 15% more performance, or 30% power reduction while achieving same performance as previously acheivable."
Here iso-power means comparing performance for the same power usage, and iso-performance means comparing power usage for the same performance.
With 5nm further improving that 7nm another 30% reduced power?
If so, we’re talking 25-35% of the current power draw for the same speed in the next 18-24 months?
I have to be wrong here... I know they use a design which doesn’t get 100% of the Benefits due to the “chiplet” arch, but still.
(Also, I think a 50% reduction followed by 30% would be 35% of current power not 15.)